TYPICAL
QUESTIONS & ANSWERS
PART - I
OBJECTIVE
TYPE QUESTIONS
Each Question carries 2 marks.
Choose correct or the best
alternative in the following:
Q.1 The NAND gate output
will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
Ans: D
The NAND gate output
will be low if the two inputs are 11
(The Truth Table of
NAND gate is shown in Table.1.1)
|
X(Input)
|
Y(Input)
|
F(Output)
|
|
0
|
0
|
1
|
|
0
|
1
|
1
|
|
1
|
0
|
1
|
|
1
|
1
|
0
|
Table 1.1 Truth Table
for NAND Gate
Q.2 What is the binary equivalent of the decimal number 368
(A) 101110000 (B) 110110000
(C) 111010000 (D) 111100000
Ans: A
The Binary equivalent of the Decimal
number 368 is 101110000
(Conversion
from Decimal number to Binary number is given in Table 1.2)
|
2
|
368
|
|
2
|
184
--- 0
|
|
2
|
92
--- 0
|
|
2
|
46
--- 0
|
|
2
|
23
--- 0
|
|
2
|
11
--- 1
|
|
2
|
5
--- 1
|
|
2
|
2
--- 1
|
|
2
|
1
--- 0
|
|
|
0
--- 1
|
Table 1.2 Conversion from Decimal number to Binary number
Q.3 The decimal equivalent of hex number 1A53 is
(A) 6793 (B) 6739
(C) 6973 (D) 6379
Ans: B
The decimal
equivalent of Hex Number 1A53 is 6739
(Conversion from Hex
Number to Decimal Number is given below)
1
A 5 3 Hexadecimal
16ł
16˛ 16š 16° Weights
(1A53)16 = (1X16ł) + (10 X 16˛) +
(5 X 16š) + (3 X 16ş)
= 4096
+ 2560 +
80 + 3
=
6739
Q.4 
(A) C 1 D (B) D C 1
(C) 1 C D (D) 1 D C
Ans:
D
(734)8
= (1 D C)16
0001
│ 1101 │ 1100
1
D C
Q.5 The simplification of the Boolean
expression 
is
(A) 0 (B) 1
(C) A (D) BC
Ans:
B
The Boolean
expression is 
+ 
is equivalent to 1
+ = 
+
+
+
+
+
= A ++ C + + B +
= (A+)(B+)(C+) = 1X1X1 = 1
Q.6 The number of control lines for a 8 to 1 multiplexer is
(A) 2 (B) 3
(C) 4 (D) 5
Ans:
B
The
number of control lines for an 8 to 1 Multiplexer is 3
(The control signals are used to
steer any one of the 8 inputs to the output)
Q.7 How many Flip-Flops are
required for mod16 counter?
(A) 5 (B) 6
(C) 3 (D) 4
Ans:
D
The number of flip-flops is required for Mod-16 Counter is 4.
(For Mod-m Counter, we need N flip-flops where N is chosen
to be the smallest number for which 2N is greater than or equal to m. In this case 24 greater than or equal to 1)
Q.8 EPROM contents can be erased by exposing it to
(A) Ultraviolet rays. (B) Infrared rays.
(C) Burst of
microwaves. (D) Intense heat radiations.
Ans:
A
EPROM contents can be erased by exposing it to Ultraviolet
rays
(The Ultraviolet light passes
through a window in the IC package to the EPROM chip where it releases stored
charges. Thus the stored contents are
erased).
Q.9 The hexadecimal number A0 has
the decimal value equivalent to
(A) 80 (B) 256
(C) 100 (D) 160
Ans: D
The
hexadecimal number A0 has the decimal value equivalent to 160
( A
0
161 160
= 10X161 + 0X160 =
160)
Q.10 The Gray code for decimal number 6
is equivalent to
(A)
1100 (B) 1001
(C) 0101 (D) 0110
Ans: C
The Gray code for decimal number 6 is equivalent to 0101
(Decimal number 6 is equivalent to binary number 0110)
+ + +
0 1 1 0
0 1 0 1
Q.11 The Boolean expression 
is equivalent to
(A) A + B (B)
(C) 
(D) A.B
Ans: A
The Boolean expression .B + A. + A.B is equivalent to
A + B
(.B + A. + A.B = B( + A ) + A.
= B +
A. {
( + A ) = 1}
= A + B {(B + A.) = B + A}
Q.12 The digital logic family which has
minimum power dissipation is
(A) TTL (B) RTL
(C) DTL (D) CMOS
Ans: D
The digital logic family which has minimum power dissipation is CMOS.
(CMOS being an unipolar logic family, occupy a very
small fraction of silicon Chip area)
Q.13 The
output of a logic gate is 1 when all its inputs are at logic 0. the gate is
either
(A) a NAND or an EX-OR (B) an OR or an EX-NOR
(C) an AND or an EX-OR (D) a NOR or an EX-NOR
Ans: D
The
output of a logic gate is 1 when all inputs are at logic 0. The gate is either
a NOR or an EX-NOR .
(The
truth tables for NOR and EX-NOR Gates are shown in fig.1(a) & 1(b).)
|
Input
A
B
|
Output
Y
|
|
0 0
|
1
|
|
0 1
|
0
|
|
1 0
|
0
|
|
1 1
|
0
|
|
Input
A
B
|
Output
Y
|
|
0 0
|
1
|
|
0
1
|
0
|
|
1 0
|
0
|
|
1 1
|
1
|
Fig.1(a) Truth Table for NOR Gate
Fig.1(b) Truth Table for EX-NOR Gate
Q.14 Data can be changed
from special code to temporal code by using
(A)
Shift registers (B) counters
(C) Combinational
circuits (D) A/D converters.
Ans: A
Data
can be changed from special code to temporal code by using Shift Registers.
(A
Register in which data gets shifted towards left or right when clock pulses are
applied is known as a Shift Register.)
Q.15 A ring counter
consisting of five Flip-Flops will have
(A) 5 states (B) 10 states
(C) 32 states (D) Infinite states.
Ans: A
A ring counter
consisting of Five Flip-Flops will have 5 states.
Q.16 The
speed of conversion is maximum in
(A)
Successive-approximation A/D converter.
(B)
Parallel-comparative A/D converter.
(C)
Counter ramp A/D converter.
(D)
Dual-slope A/D converter.
Ans: B
The speed of conversion is maximum
in Parallel-comparator A/D converter
(Speed of conversion is maximum
because the comparisons of the input voltage are carried out simultaneously.)
Q.17 The 2s complement of
the number 1101101 is
(A)
0101110 (B) 0111110
(C) 0110010 (D) 0010011
Ans: D
The
2s complement of the number 1101101 is 0010011
(1s complement of
the number 1101101 is 0010010
2s
complement of the number 1101101is 0010010 + 1 =0010011)
Q.18 The
correction to be applied in decimal adder to the generated sum is
(A) 00101 (B) 00110
(C) 01101 (D) 01010
Ans: B
The
correction to be applied in decimal adder to the generated sum is 00110.
When the four bit sum is more
than 9 then the sum is invalid. In such cases, add +6(i.e. 0110) to the four bit sum to skip the six
invalid states. If a carry is generated when adding 6, add the carry to the next four bit group .
Q.19 When
simplified with Boolean Algebra (x + y)(x + z) simplifies to
(A) x (B) x + x(y + z)
(C) x(1 + yz) (D) x + yz
Ans: D
When
simplified with Boolean Algebra (x + y)(x + z) simplifies to x + yz
[(x
+ y) (x + z)] = xx + xz + xy + yz = x + xz
+ xy + yz (xx = x)
= x(1+z) + xy + yz = x + xy + yz {(1+z) = 1}
=
x(1 + y) + yz = x + yz {(1+y) = 1}]
Q.20 The
gates required to build a half adder are
(A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate
(C) EX-OR gate and AND gate (D) Four NAND gates.
Ans: C
The gates required to build a half adder are EX-OR gate and AND gate
Fig.1(d)
shows the logic diagram of half adder.
Fig.1(d)
Logic diagram of Half Adder
Q.21 The
code where all successive numbers differ from their preceding number by single
bit is
(A) Binary
code. (B)
BCD.
(C) Excess
3. (D)
Gray.
Ans: D
The code where all successive numbers differ from their preceding number
by single bit is Gray Code.
(It is an unweighted
code. The most important characteristic of this code is that only a single bit
change occurs when going from one code number to next.)
Q.22 Which of the following is the fastest logic
(A) TTL (B) ECL
(C) CMOS (D) LSI
Ans: B
ECL is the fastest logic family of all logic
families.
(High speeds are
possible in ECL because the transistors are used in difference amplifier
configuration, in which they are never driven into saturation and thereby
the storage time is eliminated.
Q.23 If the input to T-flipflop is 100 Hz signal, the
final output of the three T-flipflops in cascade is
(A) 1000 Hz (B) 500 Hz
(C) 333 Hz (D) 12.5 Hz.
Ans: D
If the input to T-flip-flop is 100 Hz signal, the final output of the
three T-
flip-flops in
cascade is 12.5 Hz
{The final output of the three T-flip-flops in
cascade is
(T)
=
=
=12.5Hz}
Q.24 Which of the memory is volatile memory
(A) ROM (B) RAM
(C) PROM (D) EEPROM
Ans: B
RAM is a volatile memory
(Volatile memory means the
contents of the RAM get erased as soon as the
power goes off.)
Q.25 -8 is equal to signed binary
number
(A) 10001000 (B) 00001000
(C) 10000000 (D) 11000000
Ans: A
- 8 is
equal to signed binary number 10001000
(To represent negative numbers in the binary system, Digit 0 is used for
the positive sign and 1 for the negative sign. The MSB is the sign bit followed
by the magnitude bits. i.e.,
-
8 = 1000 1000
-
------- -----------------
Sign Magnitude
------- ---------------
Q.26 DeMorgans
first theorem shows the equivalence of
(A)
OR gate and Exclusive OR gate.
(B)
NOR gate and Bubbled AND gate.
(C)
NOR gate and NAND gate.
(D)
NAND gate and NOT gate
Ans: B
DeMorgans
first theorem shows the equivalence of NOR gate and Bubbled AND gate
(Logic diagrams for De Morgans First Theorem is shown in fig.1(a)
Fig.1(a) Logic Diagrams for De Morgans First
Theorem
Q.27 The digital logic family which
has the lowest propagation delay time is
(A) ECL (B) TTL
(C) CMOS (D) PMOS
Ans: A
The digital logic
family which has the lowest propagation delay time is ECL
(Lowest propagation
delay time is possible in ECL because the transistors are used in difference
amplifier configuration, in which they are never driven into saturation and
thereby the storage time is eliminated).
Q.28 The device which changes from
serial data to parallel data is
(A) COUNTER (B) MULTIPLEXER
(C) DEMULTIPLEXER (D) FLIP-FLOP
Ans: C
The
device which changes from serial data to parallel data is demultiplexer.
(A demultiplexer
takes in data from one line and directs it to any of its N outputs depending on
the status of the select inputs.)
Q.29 A device which converts BCD to
Seven Segment is called
(A) Encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer
Ans: B
A
device which converts BCD to Seven Segment is called DECODER.
(A decoder
coverts binary words into alphanumeric characters.)
Q.30 In a JK Flip-Flop, toggle means
(A)
Set Q = 1 and 
= 0.
(B)
Set Q = 0 and = 1.
(C)
Change the output to the opposite state.
(D)
No change in output.
Ans: C
In a JK Flip-Flop, toggle means
Change the output to the opposite state.
Q.31 The access time of
ROM using bipolar transistors is about
(A) 1 sec (B) 1 msec
(C) 1 μsec (D) 1 nsec.
Ans: C
The access time of ROM using bipolar transistors is about
1 
sec.
Q.32 The A/D converter
whose conversion time is independent of the number of bits is
(A) Dual slope (B) Counter type
(C) Parallel conversion (D) Successive approximation.
Ans: C
The A/D converter whose conversion time is independent of the Number of
bits is Parallel conversion.
(This type uses an array of comparators connected in parallel and
comparators compare the input voltage at a particular ratio of the reference
voltage).
Q.33 When signed numbers are used in
binary arithmetic, then which one of the following notations would have unique
representation for zero.
(A) Sign-magnitude. (B) 1s complement.
(C) 2s complement. (D)
9s complement.
Ans: A
Q.34 The logic circuit given
below (Fig.1) converts a binary code 
into
(A)
Excess-3 code. (B) Gray code.
(C) BCD code. (D) Hamming code.
Ans: B
Gray code as
X1=Y1, X2=Y1 XOR
Y2 ,
X3=Y1 XOR Y2 XOR Y3
For Y1 Y2 Y3 X1 X2 X3
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
Q.35 The logic circuit shown in the given
fig.2 can be minimised to
(A)
(B)
(C) (D)
Ans: D
As output of the logic circuit
is
Y=(X+Y)+(X+(X+Y))
(X+Y)=XY Using DE Morgans
Now this is one of input of 2nd
gate.
F=(A+X)=AX=[(XY).X]
=[(X+Y)X]=X+XY=X(Y)
=X
Q.36 In
digital ICs, Schottky transistors are preferred over normal transistors because
of their
(A) Lower Propagation delay. (B) Higher Propagation
delay.
(C) Lower Power
dissipation. (D) Higher
Power dissipation.
Ans: A
Lower propagation
delay as shottky transistors reduce the storage time delay by preventing the
transistor from going deep into saturation.
Q.37 The following switching functions are
to be implemented using a Decoder:
The
minimum configuration of the decoder should be
(A) 2
to 4 line. (B) 3 to 8 line.
(C) 4 to 16 line. (D) 5 to 32 line.
Ans: C
4 to 16 line decoder as the minterms are ranging from 1 to 14.
Q.38 A
4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns
each. The maximum possible time required
for change of state will be
(A)
15 ns. (B) 30 ns.
(C) 45 ns. (D) 60 ns.
Ans: A
15 ns because in
synchronous counter all the flip-flops change state at the same time.
Q.39 Words
having 8-bits are to be stored into computer memory. The number of lines required for writing into
memory are
(A)
1. (B) 2.
(C) 4. (D) 8.
Ans: D
Because 8-bit words
required 8 bit data lines.
Q.40 In
successive-approximation A/D converter, offset voltage equal to 
LSB is added to the
D/A converters output. This is done to
(A)
Improve the speed of operation.
(B)
Reduce the maximum quantization error.
(C)
Increase the number of bits at the output.
(D)
Increase the range of input voltage that can be converted.
Ans: B
Q.41 The decimal
equivalent of Binary number 11010 is
(A) 26. (B)
36.
(C)
16. (D) 23.
Ans: A
11010 = 1 X 24 + 1 X 2 3 + 0 X 22 + 1 X
21 = 26
Q.42 1s
complement representation of decimal number of -17 by using 8 bit
representation is
(A) 1110 1110 (B) 1101 1101
(C) 1100 1100 (D) 0001 0001
Ans: A
(17)10 = (10001)2
In 8 bit = 00010001
1's Complement = 11101110
Q.43 The
excess 3 code of decimal number 26 is
(A) 0100
1001 (B) 01011001
(C) 1000 1001 (D) 01001101
Ans: B
(26)10 in BCD is (
00100110 ) BCD
Add 011 to each BCD 01011001 for excess 3
Q.44 How
many AND gates are required to realize Y =
CD+EF+G
(A)
4 (B) 5
(C) 3 (D) 2
Ans: D
To
realize Y = CD + EF + G
Two
AND gates are required (for CD & EF).
Q.45 How
many select lines will a 16 to 1 multiplexer will have
(A) 4 (B) 3
(C) 5 (D) 1
Ans: A
In 16 to 1 MUX four select lines will be required to select
16 ( 24 ) inputs.
Q.46 How
many flip flops are required to construct a decade counter
(A) 10 (B) 3
(C) 4 (D) 2
Ans: C
Decade counter counts 10 states from 0 to 9 (
i.e. from 0000 to 1001 )
Thus
four FlipFlop's are required.
Q.47 Which
TTL logic gate is used for wired ANDing
(A) Open collector
output (B) Totem Pole
(C) Tri state output (D) ECL gates
Ans: A
Open collector output.
Q.48 CMOS
circuits consume power
(A) Equal to TTL (B)
Less than TTL
(C) Twice of TTL (D) Thrice
of TTL
Ans: B
As in CMOS one device is ON &
one is Always OFF so power consumption is low.
Q.49 In
a RAM, information can be stored
(A) By the user, number of times.
(B) By the user, only once.
(C) By the manufacturer, a number of times.
(D) By the manufacturer only once.
Ans: A
RAM is
used by the user, number of times.
Q.50 The hexadecimal
number for 
is
(A) 
(B)
(C) 
(D) 
Ans: A
(95.5)10
= (5F.8)16
Integer part Fractional part
16 95 0.5x16=8.0
16 5 15
0
5
Q.51 The octal
equivalent of 
is
(A) 
(B) 
(C) 
(D) 
Ans: C
(247)10
= (367)8
8 247
8 30 7
8 3 6
0
3
Q.52 The
chief reason why digital computers use complemented subtraction is that it
(A) Simplifies
the circuitry.
(B)
Is a very simple process.
(C)
Can handle negative numbers easily.
(D)
Avoids direct subtraction.
Ans: C
Using complement method
negative numbers can also be subtracted.
Q.53 In
a positive logic system, logic state 1 corresponds to
(A) positive voltage (B) higher voltage level
(C) zero voltage level (D)
lower voltage level
Ans: B
We decide two voltages levels for positive digital logic. Higher
voltage represents logic 1 & a lower voltage represents logic 0.
Q.54 The
commercially available 8-input multiplexer integrated circuit in the TTL family
is
(A) 7495.
(B) 74153.
(C) 74154. (D) 74151.
Ans: B
MUX integrated circuit
in TTL is 74153.
Q.55 CMOS
circuits are extensively used for ON-chip computers mainly because of their
extremely
(A) low power
dissipation. (B) high noise immunity.
(C) large packing density. (D)
low cost.
Ans: C
Because CMOS
circuits have large packing density.
Q.56 The
MSI chip 7474 is
(A) Dual edge triggered JK flip-flop (TTL).
(B) Dual edge triggered D flip-flop (CMOS).
(C) Dual edge triggered D flip-flop (TTL).
(D) Dual edge triggered JK flip-flop (CMOS).
Ans: C
MSI chip 7474 dual edge
triggered D Flip-Flop.
Q.57 Which
of the following memories stores the most number of bits
(A) a 5M
8 memory. (B) a 1M 16 memory.
(C) a 
memory. (D) a 
memory.
Ans: A
5Mx8
= 5 x 220 x 8 = 40M (max)
Q.58 The
process of entering data into a ROM is called
(A) burning in the ROM (B)
programming the ROM
(C) changing the ROM (D) charging the
ROM
Ans: B
The process of
entering data into ROM is known as programming the ROM.
Q.59 When
the set of input data to an even parity generator is 0111, the output will
be
(A) 1 (B) 0
(C) Unpredictable (D) Depends on the previous input
Ans: B
In even
parity generator if number of 1 is odd
then output will be zero.
 0
|
|
Q.60 The number 140 in
octal is equivalent to
(A) 
. (B)
.
(C) 
. (D) none of these.
Ans: A
(140)8 = (96)10
1 x 82 + 4 x 8 + 0x 1 = 64 + 32 =
96
Q.61 The NOR
gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
Ans: B, C, or D
O/P is low if any of the I/P is high
Q.62 Which
of the following is the fastest logic?
(A) ECL (B) TTL
(C) CMOS (D) LSI
Ans: A
Q.63 How
many flip-flops are required to construct mod 30 counter
(A) 5 (B) 6
(C) 4 (D) 8
Ans: A
Mod - 30 counter +/- needs 5 Flip-Flop
as 30 < 25
Mod - N counter
counts total ' N ' number of states.
To count 'N'
distinguished states we need minimum n FlipFlop's
as [N = 2n]
For eg. Mod 8 counter
requires 3 Flip-Flop's (8 = 23)
Q.64 How
many address bits are required to represent a 32 K memory
(A) 10
bits. (B) 12 bits.
(C) 14 bits. (D) 16 bits.
Ans: D
32K = 25 x
210 = 215,
Thus 15 address bits are
required, Only 16 bits can address it.
Q.65 The
number of control lines for 16 to 1 multiplexer is
(A) 2. (B) 4.
(C) 3. (D) 5.
Ans: B
As
16 = 24, 4 Select lines are required.
Q.66 Which
of following requires refreshing?
(A) SRAM. (B) DRAM.
(C) ROM. (D) EPROM.
Ans: B
Q.67 Shifting
a register content to left by one bit position is equivalent to
(A) division by two. (B)
addition by two.
(C) multiplication by
two. (D) subtraction
by two.
Ans:C
Q.68 For
JK flip flop with J=1, K=0, the output after clock pulse will be
(A) 0. (B) 1.
(C) high impedance. (D) no change.
Ans: B
Q.69 Convert decimal 153
to octal. Equivalent in octal will
be
(A) 
. (B)
.
(C) 
. (D) none of these.
Ans: A
(153)10 = (231)8
8 153 1
8 19 3
8 2 2
Q.70 The
decimal equivalent of 
is
(A) 12 (B) 16
(C) 18 (D) 20
Ans: A
(1100)2 = (12)10
Q.71 The
binary equivalent of 
is
(A) 1010
1111 (B) 1111 1010
(C) 10110011 (D) none of these
Ans: B
(FA)16 = (11111010)10
Q.72 The
output of SR flip flop when S=1, R=0 is
(A) 1 (B) 0
(C) No change (D) High impedance
Ans: A
As for the SR
flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.
Q.73 The
number of flip flops contained in IC 7490 is
(A) 2.
(B) 3.
(C) 4. (D) 10.
Ans: A
Q.74 The
number of control lines for 32 to 1 multiplexer is
(A) 4. (B) 5.
(C) 16. (D) 6.
Ans: B
The number of control
lines for 32 (25) and to select one input among them total 5 select lines are required.
Q.75 How
many two-input AND and OR gates are required to realize Y=CD+EF+G
(A) 2,2. (B) 2,3.
(C) 3,3. (D) none of these.
Ans: A
Y=CD+EF+G
Number of two input AND gates=2
Number of two input OR gates = 2
One OR gate to OR CD and EF and
next to OR of G & output of first OR gate.
Q.76 Which
of following can not be accessed randomly
(A) DRAM. (B) SRAM.
(C) ROM. (D) Magnetic tape.
Ans: D
Magnetic tape can only
be accessed sequentially.
Q.77 The
excess-3 code of decimal 7 is represented by
(A) 1100. (B)
1001.
(C) 1011. (D)
1010.
Ans: D
An
excess 3 code is always equal to the binary code +3
Q.78 When
an input signal A=11001 is applied to a NOT gate serially, its output signal is
(A) 00111. (B) 00110.
(C) 10101. (D) 11001.
Ans: B
As A=11001 is serially applied
to a NOT gate, first input applied will be LSB 00110.
Q.79 The result of adding
hexadecimal number A6 to 3A is
(A) DD. (B)
E0.
(C) F0. (D) EF.
Ans:
B
Q.80 A universal logic gate is one, which can be used to generate any
logic function. Which of the following
is a universal logic gate?
(A)
OR (B) AND
(C) XOR (D) NAND
Ans: D
NAND can generate any logic function.
Q.81 The
logic 0 level of a CMOS logic device is approximately
(A) 1.2 volts (B) 0.4 volts
(C) 5 volts (D) 0 volts
Ans: D
CMOS logic low level is 0 volts
approx.
Q.82 Karnaugh
map is used for the purpose of
(A) Reducing the electronic circuits used.
(B) To map the given Boolean
logic function.
(C) To minimize the terms in a Boolean
expression.
(D) To maximize the terms of a given a Boolean
expression.
Ans: C
Q.83 A
full adder logic circuit will have
(A) Two
inputs and one output.
(B) Three inputs and three outputs.
(C) Two inputs and two outputs.
(D) Three inputs and two outputs.
Ans:
D
A full adder circuit will add two bits and it will also
accounts the carry input generated in the previous stage. Thus three inputs and
two outputs (Sum and Carry) are there.
Q.84 An
eight stage ripple counter uses a flip-flop with propagation delay of 75
nanoseconds. The pulse width of the
strobe is 50ns. The frequency of the
input signal which can be used for proper operation of the counter is
approximately
(A)
1 MHz. (B) 500 MHz.
(C) 2 MHz. (D) 4 MHz.
Ans: A
Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50
= 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.
Q.85 The
output of a JK flipflop with asynchronous preset and clear inputs is 1. The output can be changed to 0 with one of
the following conditions.
(A) By applying J = 0, K =
0 and using a clock.
(B) By applying J = 1, K = 0 and using the clock.
(C) By applying J = 1, K = 1 and using the clock.
(D) By applying a synchronous preset input.
Ans: C
Preset state of JK Flip-Flop =1
With
J=1 K=1 and the clock next state will be complement of the present state.
Q.86 The
information in ROM is stored
(A) By the user any
number of times.
(B) By the manufacturer
during fabrication of the device.
(C)
By the user using
ultraviolet light.
(D)
By the user once and
only once.
Ans: B
Q.87 The
conversation speed of an analog to digital converter is maximum with the
following technique.
(A) Dual slope AD converter.
(B) Serial comparator AD converter.
(C) Successive approximation AD converter.
(D) Parallel comparator AD converter.
Ans: D
Q.88 A
weighted resistor digital to analog converter using N bits requires a total of
(A) N precision resistors. (B) 2N precision resistors.
(C) N + 1 precision resistors. (D) N 1 precision resistors.
Ans: A
Q.89 The 2s complement of
the number 1101110 is
(A) 0010001. (B)
0010001.
(C) 0010010. (D) None.
Ans: C
1s complement of 1101110 is = 0010001
Thus 2s complement of 1101110 is =
0010001 + 1 = 0010010
Q.90 The
decimal equivalent of Binary number 10101 is
(A) 21 (B) 31
(C) 26 (D) 28
Ans: A
1x24
+ 0x23 +1x22 +0x21 + 1x20
= 16 + 0 + 4 + 0
+ 1 = 21.
Q.91 How
many two input AND gates and two input OR gates are required to realize
Y =
BD+CE+AB
(A) 1, 1 (B) 4, 2
(C) 3, 2 (D) 2, 3
Ans: A
There are three product terms, so three AND
gates of two inputs are required.
As only two
input OR gates are available, so two OR gates are required to get the logical
sum of three product terms.
Q.92 How
many select lines will a 32:1 multiplexer will have
(A) 5.
(B) 8.
(C) 9. (D) 11.
Ans: A
For 32 inputs, 5 select
lines will be required, as 25 = 32.
Q.93 How
many address bits are required to represent 4K memory
(A) 5 bits. (B) 12 bits.
(C) 8 bits. (D) 10 bits.
Ans: B
For representing 4K memory, 12 address bits
are required as
4K =
22 x 210 = 212 (1K = 1024 = 210)
Q.94 For
JK flipflop J = 0, K=1, the output after clock pulse will be
(A) 1. (B) no change.
(C) 0. (D) high impedance.
Ans: C
J=0, K=1, these inputs will reset the flip-flop after the clock
pulse. So whatever be the previous output, the next state will be 0.
Q.95 Which
of following are known as universal gates
(A) NAND & NOR. (B) AND & OR.
(C) XOR & OR. (D) None.
Ans: A
NAND & NOR are known as universal gates, because any digital
circuit can be realized completely by using either of these two gates.
Q.96 Which
of the following memories stores the most number of bits
(A) 
memory. (B) 
memory.
(C) 
memory. (D) 
memory.
Ans: C
32M x 8 stores most number of bits
25
x 220 = 225 (1M = 220 = 1K x 1K
= 210 x 210)
Q.97 Which
of following consume minimum power
(A) TTL. (B) CMOS.
(C) DTL. (D) RTL.
Ans: B
CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS
transistors are connected in complimentary mode, such that one device is ON
& one is OFF.
PART II
NUMERICALS
Q.1 Convert the octal number 7401 to Binary. (4)
Ans:
Conversion of
Octal number 7401 to Binary:
Each octal digit represents 3 binary digits. To convert an octal number to binary number,
each octal digit is replaced by its 3 digit binary equivalent shown below.
7 4 0 1
111 100
000 001
Thus, (7401)8 =
(111100000001)2
Q.2 Find
the hex sum of 
. (4)
Ans:
Hex Sum of (93)16
+ (DE)16
Convert Hexadecimal numbers 93 and DE to
its binary equivalent shown below:-
93
→ 10010011
DE → 11011110
----------------
101110001 → 171
-----------------
Thus (93)16 + (DE)16
= (171)16
Q.3
Perform
2s complement subtraction of 
. (4)
Ans:
2s Complements Subtraction
of (7)10 (11)10
First convert the
decimal numbers 7 and 11 to its binary equivalents.
(7)10 = (0111)2
(11)10 = (1011)2 in 4-bit system
Then
find out the 2s complement for 1011 i.e.,
1s Complement of 1011 is 0100
2s Complement of 1011 is 0101
So, (7)10 (11)10 =
0111
0101
---------
1100
---------
Since there is no
carry over flow occurring in the summation, the result is a negative number, to
find out its magnitude, 2s Complement of the result must be found.
2s Complement of 1100 is 0011
1
--------
0100
--------
Here the answer is (-4)10 (or)
in 2s complement it is 1100.
Q.4 What is the Gray equivalent
of 
. (2)
Ans:
Gray equivalent of (25)10
The binary equivalent of Decimal
number 25 is (00100101)2
1. The left most bit (MSB) in gray code
is the same as the left most in binary
2.
Add the left most bit to the adjacent bit
3. Add the next adjacent pair and so on.,
Discard if we get a carry.
0 + 0 + 1 + 0 + 0 + 1 + 0 + 1
0 0
1 1
0 1 1 1 Gray Number
Q.5 Evaluate x = 
using the convention A
= True and B = False. (4)
Ans:
Evaluate x =.B + 
= B + C (+
) (Since 
= + by using
Demorgans Law)
=.B + C . + C.
By using the given convention, A
= True = 1; B = False = 0
=
.0 + C.+ C. = 0 + 0 + C. = C.
Q.6 Simplify
the Boolean expression F = C(B + C)(A + B + C). (6)
Ans:
Simplify the Boolean
Expression F = C (B +C) (A+B+C)
F = C (B+C) (A+B+C)
= CB + CC [(A+B+C)]
= CB + C [(A+B+C)] ( CC = C)
= CBA + CBB + CBC + CA
+ CB + CC
= ABC + CB + CB + CA +
CB + CC ( CBB =CB & CBC = CB)
= ABC + CB + CA +
C ( CB+CB+CB = CB; CC = C)
= ABC + BC + C (1+A)
= ABC + BC + C (1+A = 1)
= ABC + C (1+B)
= ABC + C
( 1+B = 1)
= C (1+AB) = C {(1+AB)=1}
Q.7 Simplify
the following expression into sum of products using Karnaugh map 
(7)
Ans:
Simplification of the following expression into sum of
products using Karnaugh
Map:
F(A,B,C,D) = S (1,3,4,5,6,7,9,12,13)
Karnaugh Map for the expression
F(A,B,C,D) = S
(1,3,4,5,6,7,9,12,13)
is shown in Fig.4(a). The grouping of cells is also shown in the
Figure.
The equations for (1)
is B; (2) is D; (3) is D; (4) is B
Hence, the Simplified
Expression for the above Karnaugh map is
F(A,B,C,D) = B+D+D+B
= (B + D) +( B + D)
Q.8 Simplify and draw the logic
diagram for the given expression
. (7)
Ans:
Simplification
of the logic expression
F = 
+
C + B+ A
+ AC
F = +C + B+ A+ AC
F = ++ + (+)C +B+ A (+) + AC
( = ++ and = + by using Demorgans Law)
= +++C +C + B + A+ A+ AC
=+C++C ++ A+B+A+ AC
= (1+C)+(1 + C) +(1 + A) + B+ A+ AC
= +++B+ A+ AC { (1+C) = 1 and (1+A) = 1}
= ( + A) +(1 + AC) +(1+B)
= (+)++ { ( + A) = (+); (1+AC) = 1 and (1+B) =1}
F = (++) (+=)
The logic diagram for
the simplified expression F = (++) is given in fig.5(a)
Fig.5(a) Logic diagram for the expression F = (++)
Q.9 Determine the binary numbers represented
by the following decimal numbers. (6)
(i) 25.5
(ii) 10.625 (iiii) 0.6875
Ans:
(i) Conversion of
decimal number 25.5 into binary number:
Here integer part is 25 and fractional part is 0.5. First convert the integer part 25 into
its
equivalent binary number i.e., divide 25 by 2 till the quotient becomes
0 shown in table 2(a)
|
|
Quotient
|
Remainder
|
|
|
12
|
 1
|
|
|
6
|
 0
|
|
|
3
|
0
|
|
|
1
|
1
|
|
|
0
|
1
|
Table 2(a)
So, integer part (25)10 is equivalent to the binary number
11001. Next convert fractional part 0.5 into binary form i.e., multiply the
fractional part 0.5 by 2 till you get remainder as 0
0.5
X 2
------
1.0 Remainder
1
(Quotient)
The decimal fractional part 0.5 is
equivalent to binary number 0.1. Hence,
the decimal number 25.5 is equal to the binary number 11001.1
(ii)
Conversion of decimal number 10.625 into binary number:
Here integer part is 10 and fractional part is 0.625. First convert the
decimal number 10 into its equivalent binary number i.e., divide 10 by 2 till
the quotient becomes 0 shown in table 2(b)
|
|
Quotient
|
Remainder
|
|
|
5
|
0
|
|
|
2
|
1
|
|
|
1
|
0
|
|
|
0
|
1
|
Table 2(b)
So, the integer part 10 is equal
to binary number 1010. Next convert the
decimal fractional part 0.625 into its binary form i.e., multiply 0.625 by 2
till the remainder becomes 0
0.625 0.250 0.50
X 2 X 2 X 2
------- -------- -------
1.250 0.50
1.0 (Remainder)
1 0 1 (Quotient)
So, the decimal fractional part 0.625 is equal to binary number 0.101.
Hence the decimal number 10.625 is equal to binary number 1010.101.
(iii)Conversion of fractional number 0.6875 into its equivalent binary number:
Multiply the fractional number 0.6875 by 2 till the remainder becomes 0
i.e.,
0.6875 0.3750 0.75 0.5
X
2 X 2 X 2 X 2
----------- --------- -------- ------
1.3750 0.75 1.5
1.0 (Remainder)
1 0 1 1 (Quotient)
So, the decimal fractional number 0.6875 is equal to binary number
0.1011.
Q.10 Perform the
following subtractions using 2s complement method. (8)
(i) 01000 01001 (ii)
01100 00011 (iii) 0011.1001
0001.1110
Ans:
(i) Subtraction of 01000-01001: 1s complement of 01001 is 10110 and 2s complement is
10110+ 1 =10111. Hence
01000 = 01000
- 01001 =
+10111 (2's complement)
-------------------------
11111 (Summation)
-------------------------
Since the MSB of the
sum is 1, which means the result is negative and it is in 2's complement form.
So, 2's complement of 1111 =00001= (1)10. Therefore, the result is 1.
(ii) Subtraction of 01100-00011:
1s complement of 00011 is 11100 and 2s complement
is 11100 + 1 = 11101. Hence
01100 =
01100
00011
= + 11101 (2's complement)
--------------------------------------------------
1 01001 = + 9
Ignore
--------------------------------------------------
If a final carry is generated discard the
carry and the answer is given by the remaining bits
Which
is positive i.e., (1001)2 = (+ 9)10
(iii) Subtraction of 0011.1001 0001.1110: 1s complement of 0001.1110
is 1110.0001 and its 2s complement is 1110.0010.
0011.1001 = 0011.1001
-
0001.1110 = + 1110.1011 (2s complement)
-------------------------------------------
1 0001.101I = + 1 .68625
Ignore
If a final carry is generated discard the carry and the
answer is given by the remaining bits which is positive i.e., (0001.1011)2
= (+ 1.68625)10
Q.11 Simplify the expressions using Boolean postulates (9)
(i) 
(ii) Y = (A
+ B)( + C)(B + C)
(iii) XY + 
+ X
Z (XY + Z)
Ans:
(i)
= 
=
=
(Because 
= 
and
= 
)
= 
= 
(Because XX=X)
=
= 
(Because
(1+Y=1)
=
(Because 
= 
+ )
=
=
(Because = )
=
=
=
= 
(Because 
= 1)
=
= 0 (Because 1
=1)
(ii) Y = (A + B)( + C)(B + C)
Y = (A + B)( + C)(B + C)
= (A + AC + B+ BC) (B + C)
= (AC + B + BC) (B + C) (Because A = 0)
= ABC + BB + BBC + ACC + BC + BCC
= ABC + B + BC + AC + BC + BC
(Because BB = B)
= ABC + AC + B + B
+ BC
(Because BC + BC = BC)
=AC (B+1) + B + BC (+1)
= AC + B + BC
(Because
B + 1 = 1 and + 1 = 1)
= AC + B + BC (A +) (Because A + = 1)
= AC + B + BCA + BC
= AC(1 + B) + B(1 + C)
= AC + B
{Because (1 + B) = 1 and (1 + C) =1}
(iii) XY + + XZ (XY + Z)
= XY + + XZ (XY + Z)
=
XY + + XXYZ + XZ Z
= XY + + XZ (Because Y = 0 & ZZ
= Z)
= XY + + 
+ XZ (Because = + )
= + XY + + XZ
= + X (Y +Z) +
= + X (Y +Z) + (Because Y +Z = Y +Z)
= + X Y (Z+) + XZ + (Because Z+ =1)
= + X Y Z + XY + XZ +
= + XZ (1+ Y) + (1+XY)
= + XZ + (Because 1+ Y = 1
&1+XY = 1)
= + XZ) +
=( + Z) + (Because + XZ = + Z
= +( Z + )
=+1 (Because Z + = 1)
=1 (Because +1 = 1)
Q.12 Minimize the logic function
. Use Karnaugh
map. Draw logic circuit for the
simplified function. (9)
Ans:
Fig. 4(a) shows the
Karnaugh map. Since the expression has 4
variables, the map has 16 cells. The digit 1 has been written in the cells
having a term in the given expression. The decimal number has been added as
subscript to indicate the binary number for the concerned cell. The term ABC cannot be combined with any other cell. So this term
will appear as such in the final expression.
There are four groupings of 4 cells each. These correspond to the min
terms (0, 1, 2, 3), (0, 1, 8, 9), (1, 3,5,7) and (1, 3, 9, 11). These are shown
in the map. Since all the terms (except 14) have been included in groups of 4
cells, there is no need to form groups of two cells.
The simplified expression is Y (A,B,C,D)
= ABC+++D+D
Fig.4 (b) shows the logic diagram
for the simplified expression
Y (A,B, C, D) =
ABC+++D+D
Fig.4(b) Logic diagram for Y
Q.13 Simplify
the given expression to its Sum of
Products (SOP) form. Draw the logic circuit for the simplified SOP
function 
(5)
Ans:
Simplification of given expression
Y
= (A + B) (A + ) C + (B + ) + B + ABC
in some of products (SOP) form:-
Y
= (A + B) (A + ) C + (B + ) + B + ABC
=(A + B) (A + ) C + (B + ) + B + ABC
=(A + B) (A + +)C + (B + ) + B + ABC
=(A + B) (1+)C + (B + ) + B + ABC (Because A + = 1)
= (A
+ B) (C+C) + B + + B + ABC
= (A + B) (C+C) + B + + B + ABC
=AC +
AC + BC + BC + B + + B + ABC
= AC + AC( + B) + BC + 0 + B + + B (Because B = 0)
= AC
+ AC+ BC+ B + (Because + B = 1)
= AC+ BC+ B + (Because AC + AC = AC)
= C (A+ B) + (B + )
Fig.4(c) Simplified Logic Circuit
Q.14 Design
a 8 to 1 multiplexer by using the four variable function given by 
. (10)
Ans:
Design of 8 to 1
Multiplexer:
This
is a four-variable function and therefore we need a multiplexer with three
selection lines and eight inputs. We choose to apply variables B, C, and
D to the selection lines. This is shown inTable 8.1. The first half of the minterms are associated
with A' and the second half with A. By circling the minterms of
the function and applying the rules for finding values for the multiplexer
inputs, the implementation shown in Table.8.2.
The given function
can be implemented with a 8-to-1 multiplexer as shown in fig.8(a). Three of the variables, B, C and D are
applied to the selection lines in that order i.e., B is connected to s2,
C to s1 and D to s0. The
inputs of the multiplexer are 0, 1, A and A.
When BCD = 000,001 & 111 output F = 1 since I0 & I8
= 1 for BCD(000), I1 = 1and I9 =1 respectively. Therefore, minterms m0 = A B C
m1 = A B C, m8 = A, B, C and
m9 = A B
C produce a 1 output. When BCD = 010,
101 and 110, output F = 0, since I2, I5 and I6
respectively are equal to 0.
|
Minterm
|
A B C D
|
F
|
|
0
|
0 0 0 0
|
1
|
|
1
|
0 0 0 1
|
1
|
|
2
|
0 0 1 0
|
0
|
|
3
|
0 0 1 1
|
 1
|
|
4
|
0 1 0 0
|
1
|
|
5
|
0 1 0 1
|
0
|
|
6
|
0 1 1 0
|
0
|
|
7
|
0 1 1 1
|
0
|
|
8
|
1 0 0 0
|
1
|
|
9
|
1 0 0 1
|
1
|
|
10
|
1 0 1 0
|
0
|
|
11
|
1 0 1 1
|
0
|
|
12
|
1 1 0 0
|
0
|
|
13
|
1 1 0 1
|
0
|
|
14
|
1 1 1 0
|
0
|
|
15
|
1 1 1
1
|
1
|
Table
.8.1 Truth Table for 8-1 Multiplexer
Table
8.2 Implementation Table for 8 to 1 MUX
Fig.8(a) Logic circuit for 8-to-1
Multiplexer
Q.15 Convert
the decimal number 82.67 to its binary, hexadecimal and octal equivalents. (6)
Ans:
(i)Conversion of Decimal
number 82.67 to its Binary Equivalent
Considering the integer part 82 and finding
its binary equivalent
|
2
|
82
|
|
2
|
 41 Remainder
----- 0 (LSB)
|
|
2
|
20 Remainder ----- 1
|
|
2
|
10 Remainder ----- 0
|
|
2
|
5 Remainder ------0
|
|
2
|
2 Remainder ----- 1
|
|
2
|
1 Remainder ---- 0
|
|
|
0 Remainder ---- 1 (MSB)
|
The
Binary equivalent is (1010010)2
Now
taking the fractional part i.e., 0.67
|
Fraction
|
Fraction
X 2
|
Remainder
New
Fraction
|
 Integer
|
|
0.67
|
1.34
|
0.34
|
1
|
|
0.34
|
0.68
|
0.68
|
0
|
|
0.68
|
1.36
|
0.36
|
1
|
|
0.36
|
0.72
|
0.72
|
0
|
|
0.72
|
1.44
|
0.44
|
1
|
|
0.44
|
0.88
|
0.88
|
0
|
|
0.88
|
1.76
|
0.76
|
1
|
|
0.76
|
1.52
|
0.52
|
1
|
It is seen that, it is not possible to get a
zero as remainder even after 8 stages. The process
continued further on an approximation can be
made and the process is terminated here.
The binary equivalent is
0.10101011
Therefore, the binary equivalent
of decimal number 82.67 is (1010010.10101011)2
(ii)Conversion of the binary
equivalent of decimal number 82.67 into Hexadecimal:
The binary equivalent
of decimal number 82.67 is (1010010.10101011)2
Convert each 4-bit
binary into an equivalent hexadecimal number i.e.
0101 0010
.1010 1011
5 2
A
B
Therefore, the hexadecimal
equivalent of decimal number 82.67 is
(52.AB)16
(iii)Conversioin of the binary
equivalent of decimal number 82.67 into Octal number:
The binary equivalent of decimal number 82.67 is
(1010010.10101011)2
Convert each 3-bit binary into an equivalent octal number
i.e.
001
010 010 .101
010 110
1 2
2 .
5 2 6
Therefore, the Octal
equivalent of decimal number 82.67 is (122.526)8
Q.16 Add
20 and (-15) using 2s complement. (4)
Ans:
Addition of 20 and (-15) using
2s Complement:
|
2
|
20
|
|
2
|
10 Remainder ----- 0 (LSB)
|
|
2
|
5 Remainder ----- 0
|
|
2
|
2 Remainder ----- 1
|
|
2
|
1 Remainder ------0
|
|
|
0 Remainder ----- 1(MSB)
|
|
|
|
|
2
|
16
|
|
2
|
8 Remainder ----- 0 (LSB)
|
|
2
|
4
Remainder ----- 0
|
|
2
|
2 Remainder ----- 0
|
|
2
|
1 Remainder ------0
|
|
|
0 Remainder ----- 1(MSB)
|
(20)10 = 1 0 1 0 0
(16)10 =
1 0 0 0 0
(-16)10 = 0 1 1 1 1(1s Complement)
+1(2s Complement)
---------------------
1 0 0 0 0
---------------------
Therefore, 20
= 1
0 1 0 0
-16 =
1 0 0
0 0
-----------------------------
1 0
0 1 0 0
(Neglect)
--------------------------------
Since
the MSB of the sum is 0, which means the
result is positive i.e +4
Q.17 Add
648 and 487 in BCD code. (4)
Ans:
Addition of 648 and 487 in BCD
Code:
6 4
8 = 0 1 1 0
0 1 0 0 1 0 0 0
4 8
7 = 0 1 0 0
1 0 0 0 0 1 1 1
--------------------------------------------------
1 0 1 0 1 1 0 0
1 1 1 1
10 12 15
--------------------------------------------------
In
the above problem all the three groups are invalid, because the four bit sum is
more than 9. In such cases, add +6(i.e. 0110) to the four bit sum to skip the
six invalid states. If a carry is generated when adding 6, add the carry to the
next four bit group i.e.
6 4
8 = 0 1 1 0
0 1 0 0 1 0 0 0
4 8
7 = 0 1 0 0
1 0 0 0 0 1 1 1
--------------------------------------------------
1 0 1 0 1 1 0 0
1 1 1 1
0 1 1
0 0 1 1 0 0 1 1 0
1 1 1 1
1 1 1 1
------------------------------------------------------
0001 0 0 0
1 0 0 1 1 0 1 0
1
1 1 3 5
-------------------------------------------------------
Addition of 648 and 487 in BCD Code is
1135.
Q.18 Prove
the following Boolean identities. (4)
(i) XY + YZ + Z = XY + Z
(ii) 
Ans:
(i) Prove the Boolean Identity
XY + YZ + Z = XY + Z
L.H.S = XY + YZ + Z
= XY(Z+ ) + YZ + Z (Z + 
= 1)
= XYZ + XY+ YZ + Z
= YZ(1+X) + XY+Z
= YZ + XY+Z (
1+X = 1)
= Z (Y+) + XY
= Z + XY( Y+=1)
= Z + XY(Z + XY= Z + XY)
= R.H.S (Hence Proved)
(ii)
Prove the Boolean Identity A B + B + = + B
R.H.S = + B
= (B + ) + B (A + ) (B + = 1 & A + = 1)
= (B + ) + B (A + )
= B + + B A + B
= B + 
+ B A (B + B = B)
= L.H.S (Hence Proved)
Q.19 For
, write the truth table. Simplify using Karnaugh map and
realize the function using NAND gates only. (10)
Ans:
Simplification of
Logic Function F = A B C + B D + B C
(i)The
Truth Table is given in Table 4.1
|
Inputs
A B C D
|
Output
(F)
|
|
0 0 0 0
|
0
|
|
0 0 0 1
|
0
|
|
0 0 1 0
|
0
|
|
0 0 1 1
|
0
|
|
0 1 0 0
|
0
|
|
0 1 0 1
|
1
|
|
0 1 1 0
|
1
|
|
0 1 1 1
|
1
|
|
1 0 0 0
|
0
|
|
1 0 0 1
|
0
|
|
1 0 1 0
|
0
|
|
1 0 1 1
|
0
|
|
1 1 0 0
|
0
|
|
1 1 0 1
|
1
|
|
1 1 1 0
|
1
|
|
1 1 1 1
|
1
|
Table 4.1
(ii) The Karnaugh Map is shown in fig.4(a).
The simplified expression is F = BC + BD
(iii)
The NAND-NAND Realization is shown in fig.4(b)
Fig.
4(b) NAND-NAND Realization
Q.20 Determine
the analog output voltage of 6-bit DAC (R-2R ladder network) with Vref
as 5V when the digital input is 011100. (10)
Ans:
For 6-bit R-2R DAC ladder
network, the output voltage is given by
Given Data : VR =
5V, n = 6, a5=0, a4=1,a3=1,a2=1,a1=0,a0=0
= 2.1875 V
Q.21 Solve
the following equations for X (6)
(i) 
(ii) 65.53510 = X16
Ans:
(i) Solve the equation 23.610 =
X2 for X
23.610 = X2
In
order to find X, convert the Decimal number 23.610 into its Binary
form.
First
take the decimal integer part 23 to convert into its equivalent binary form
|
2
|
 23
|
|
2
|
11 ------- 1
|
|
2
|
5 --------1
|
|
2
|
2 --------1
|
|
2
|
1 --------0
|
|
|
0 --------1
|
Hence
2310 = 101112
Next
take the decimal fractional part 0.6 to convert into its equivalent binary form.
|
Fraction
|
Fraction
X 2
|
Remainder
new
fraction
|
 Integer
|
|
0.6
|
1.2
|
0.2
|
1
|
|
0.2
|
0.4
|
0.4
|
0
|
|
0.4
|
0.8
|
0.8
|
0
|
|
0.8
|
1.6
|
0.6
|
1
|
|
0.6
|
1.2
|
0.2
|
1
|
|
0.2
|
0.4
|
0.4
|
0
|
|
0.4
|
0.8
|
0.8
|
0
|
It is seen that it is not possible to get a zero as remainder even after
7 stages. The process can be continued
further or an approximation can be made and the process terminated here.
The binary equivalent is 0.1001100.
Hence
23.610 = 10111.10011002.
(ii) In order to find X, convert the
Decimal number 65.535 into its equivalent Hexadecimal form. First taking the
integer part 65 to convert into its equivalent Hexadecimal form.
|
16
|
 65
|
|
16
|
4 ---- 1
|
|
|
 0 ---- 4
|
Hence
6510 = 4116
Next
take the decimal fractional part 0.6 to convert into its equivalent binary form.
|
Fraction
|
Fraction X 16
|
Remainder
new
fraction
|
Integer
|
|
0.535
|
8.56
|
0.56
|
8
|
|
0.56
|
8.96
|
0.96
|
8
|
|
0.96
|
15.36
|
0.36
|
15 (F)
|
|
0.36
|
5.76
|
0.76
|
5
|
|
0.76
|
12.16
|
0.16
|
12(C)
|
|
0.16
|
2.56
|
0.56
|
2
|
|
0.56
|
8.96
|
0.96
|
8
|
It is seen that it is not possible to get a zero as remainder even after
7 stages. The process can be continued
further or an approximation can be made and the process terminated here.
The Hexadecimal equivalent is 0.88F5C28.
Hence 65.53510 = 41.88F5C2816.
Q.22 Perform the following additions using 2s complement (5)
(i) -20 to +26 (ii) +25 to -15
Ans:
(i)
First convert the two numbers 20
and 26 into its 8-bit binary equivalent and
find out the
2s complement of 20, then add -20
to +26.
20
= 0 0 0 1 0 1 0 0 (8-bit binary
equivalent of 20)
= 1 1 1 0 1 0 1 1 (1s
complement)
+1
-------------------------------
= -20 = 1 1 1 0 1 1 0 0 (2s complement of 20)
+26 = 0 0 0 1 1 0 1 0 (8-bit
binary equivalent of 26)
-----------------------------
Addition of -20 to +26
= +6 = 0 0
0 0 0 1 1 0
-----------------------------
Hence -20 to +26 = (6)10
= (0110)2.
(ii)
First convert the two numbers 25
and 15 into its 8-bit binary equivalent and find out
the 2s complement of 15, then add +25 to -15.
15 = 0 0 0 0 1 1 1 1 (8-bit binary equivalent of
15)
= 1 1 1
1 0 0 0 0 (1s complement)
+1
------------------------------
= -15
= 1 1 1 1 0 0 0 1 (2s complement of 15)
+25 = 0 0 0 1 1 0 0 1 (8-bit binary equivalent of 25)
------------------------------
Addition of -15 to +25
= +10 = 0 0 0 0
1 0 1 0
-------------------------------
Hence -15 to +25 = (10)10
= (1010)2.
Q.23 (i)
Convert the decimal number 430 to Excess-3 code: (6)
(ii) Convert the binary number
10110 to Gray code:
Ans:
(i)
Excess 3 is a digital code
obtained by adding 3 to each decimal digit and then converting the result to
four bit binary. It is an unweighted
code i.e., no weights can be assigned to any of the four digit positions.
4 3 0
+
3 + 3 + 3
-----------------------------
7 6 3
0111 0110
0011 (Excess-3 Code)
--------------------------------
(ii)
The rules for changing binary
number 10110 into its equivalent Gray code are, the left
most
bit (MSB) in Gray code i.e., 1 is the same as the left most bit in binary and
add
the left most bit (1) to the adjacent bit (0) then add the next adjacent pair
and discard the carry. Continue this
process till completion.
+ + + +
1 0
1 1 0
1 1 1 0 1
Hence
Gray equivalent of Binary number 10110 is 11101.
Q.24 Verify
that the following operations are commutative but not associative (6)
(i) NAND (ii) NOR
Ans:
(i) Commutative Law is = 
. To verify whether the NAND operation is Commutative or not,
prepare truth table shown in Table No.3.1
|
A
|
B
|
|
|
|
0
|
0
|
1
|
1
|
|
0
|
1
|
1
|
1
|
|
1
|
0
|
1
|
1
|
|
1
|
1
|
0
|
0
|
Table No.3.1
From the Table No.3.1, we
observe that the last two columns are identical, which means
=
Associative
Law is 
= 
To verify whether the NAND operation is Associative or not, prepare truth
table shown in Table No.3.2
|
A
|
B
|
C
|
|
|
|
0
|
0
|
0
|
1
|
1
|
|
0
|
0
|
1
|
1
|
0
|
|
0
|
1
|
0
|
1
|
1
|
|
0
|
1
|
1
|
1
|
0
|
|
1
|
0
|
0
|
0
|
1
|
|
1
|
0
|
1
|
0
|
0
|
|
1
|
1
|
0
|
0
|
1
|
|
1
|
1
|
1
|
1
|
1
|
Table
No.3.2
From the Table No.3.2, we
observe that the last two columns are not identical, which means
≠
(ii) Commutative Law is 
= 
. To verify whether the NOR operation is Commutative or not,
prepare truth table shown in Table No.3.3
|
A
|
B
|
|
|
|
0
|
0
|
1
|
1
|
|
0
|
1
|
0
|
0
|
|
1
|
0
|
0
|
0
|
|
1
|
1
|
1
|
1
|
Table No.3.3
From
the Table No.3.3, we observe that the last two columns are identical, which
means
=
Associative
Law is 
= 
To
verify whether the NOR operation is Associative or not, prepare truth table
shown in Table No.3.4
|
A
|
B
|
C
|
|
|
|
0
|
0
|
0
|
0
|
0
|
|
0
|
0
|
1
|
1
|
0
|
|
0
|
1
|
0
|
1
|
1
|
|
0
|
1
|
1
|
1
|
0
|
|
1
|
0
|
0
|
0
|
1
|
|
1
|
0
|
1
|
0
|
0
|
|
1
|
1
|
0
|
0
|
1
|
|
1
|
1
|
1
|
0
|
0
|
Table No.3.4
From
the Table No.3.4, we observe that the last two columns are not identical, which
means
≠
Q.25 Prove
the following equations using the
Boolean algebraic theorems: (5)
(i) A +.B + A .= A + B (ii) BC + AC + AB + ABC = AB + BC + AC
Ans:
(i) Given
equation is A +.B + A. = A + B
L.H.S. = A +.B + A.
= (A + A.) + .B
= A (1+) + .B
= A + .B ( 1+ =1)
= (A + ) (A + B)
= (A +
B) (A + = 1)
= R.H.S
Hence
Proved
(ii) Given equation is BC + AC + AB + ABC = AB + BC + AC
L.H.S
= BC + AC + AB + ABC
= BC + AC + AB + ABC
= BC + AC + AB (C +)
= BC + AC + AB ( C + = 1)
= BC + A (B +C)
= BC + A (B + C) (B +C = B + C)
= BC + A B + AC
= C (A + B) + A B + AC
= C (A + B) + A B + AC (A + B = A + B)
= AC + BC + AB + AC
= AB + BC + AC (AC + AC = AC)
= R.H.S
Hence
Proved
Q.26 A staircase light is controlled
by two switches one at the top of the stairs and another at the bottom of stairs (5)
(i)
Make a truth table for this system.
(ii) Write the logic equation is SOP form.
(iii) Realize the circuit using AND-OR gates.
Ans:
A staircase light is controlled by two switches S1 and S2,
one at the top of the stairs and another at the bottom of the stairs. The
circuit diagram of the system is shown in fig.4(a).
Fig.4(a) Circuit diagram
(i) The truth table for the system is given
in truth table 4.1
|
S1
|
S2
|
L
|
|
0
|
0
|
0
|
|
0
|
1
|
1
|
|
1
|
0
|
1
|
|
1
|
1
|
0
|
Table 4.1
(ii) The logic equation for the system
is given by L = 
S2 + S1 
(iii) Realization of the circuit using
AND-OR gates is shown in fig 4(b)
Fig.4(b)
Logic Diagram for the system
Q.27 Minimize the
following logic function using K-maps and realize using NAND and NOR gates. 
(9)
Ans:
Minimization of the logic function F(A, B, C, D) = ∑
m(1,3,5,8,9,11.15) + d(2,13) using K-maps and Realization using NAND and NOR
Gates
(i)
Karnaugh Map for the
logic function is given in table 4.1
The minimized logic expression in SOP form
is F = A + D + 
D + AD
The
minimized logic expression in POS form is F = (A + +) (+D) (+D) (A+D)
(ii) Realization of the
expression using NAND gates:
The minimized logic
expression in SOP form is F = A + D + D + AD and the logic diagram for the simplified
expression is given in fig.4(c)
Fig.4(c) Logic Diagram
(iii) Realization of the expression using
NOR gates:
The minimized logic
expression in POS form is F = (A + +) (+D) (+D) (A+D) and the logic diagram for the simplified
expression is given in fig.4(d)
Fig.4(d) Logic Diagram
Q.28 Design a 4 to 1 Multiplexer by
using the three variable function given by 
(7)
Ans:
Design of 4 to 1 Multiplexer by using the
three variable function given by
F(A,B,C) = ∑ m(1,3,5,6)
The function F(A,B,C) = ∑ m(1,3,5,6) can be
implemented with a 4-to-1 multiplexer as shown in Fig.7(a). Two of the
variables, B and C are applied to the selection lines in that order, i.e., B
is connected to S1 and C to S0. The
inputs of the multiplexer are 0, I, A, and A'.
When BC = 00, output F = 0 since I0
= 0. Therefore, both minterms m0 = A' B' C' and
m4 = A B' C'
produce a 0 output, since the output is 0 when BC = 00 regardless of the
value of A.
When BC = 01,
output F = 1, since I1 = 1. Therefore, both minterms
m1 =A' B'C and
m5 = AB'C produce
a 1 output, since the output is 1. when BC = 01 regardless of the value
of A.
When BC = 10,
input I2 is selected. Since A is connected to this
input, the output will be equal to 1 only for minterm m6 = ABC',
but not for minterm m2 = A' BC', because when
A' = I, then A =
0, and since I2 = 0, we have F = 0.
Finally, when BC =
11, input I3 is selected. Since A' is connected to
this input, the output will be equal to 1 only for minterm m3 =
A' BC, but not for m7 = ABC. This is given in
the Truth Table shown in Table No 7.1
|
Minterm
|
A
|
B
|
C
|
F
|
|
0
|
0
|
0
|
0
|
0
|
|
1
|
0
|
0
|
1
|
1
|
|
2
|
0
|
1
|
0
|
0
|
|
3
|
0
|
1
|
1
|
1
|
|
4
|
1
|
0
|
0
|
0
|
|
5
|
1
|
0
|
1
|
1
|
|
6
|
1
|
1
|
0
|
1
|
|
7
|
1
|
1
|
1
|
0
|
Table 7.1 Truth Table
Fig.7(a) Implementation Table
Fig.7(b) Logic Diagram of 4X1 Multiplexer
Q.29 Find the conversion time of a
Successive Approximation A/D converter which uses a 2 MHz clock and a 5-bit
binary ladder containing 8V reference. What is the Conversion Rate? (4)
Ans:
Given
data:
Frequency of the clock (F) = 2 MHZ
Number of bits (n) = 5
(i) Conversion Time (T) = 
= 
= 2.5 
(ii) Conversion Rate = 
= 
= 400,000
conversions/sec
Q.30 A
6-bit R-2R ladder D/A converter has a reference voltage of 6.5V. It meets
standard linearity. Find
(i) The Resolution in Percent.
(ii) The output voltage
for the word 011100. (4)
Ans:
Given
Data Number of Bits (n) = 6
Reference Voltage
(VR) = 6.5 V
For
R-2R Ladder D/A Converter,
(i)The Resolution in Percent is given by 
%
(ii)The Output
Voltage (VO ) of 6-bit R-2R Ladder D/A Converter for the word 011100
is given by
V.
Q.31 Convert 2222 in Hexadecimal number. (4)
Ans:
2222
16 138 14
16 8 10 =8AE
0 8
Q.32 Subtract 27
from 68 using 2s complements. (6)
Ans:
68-(-27)=68-(-27)using 2s complement
2s
complement representation of 68=01000100(64+4)
2s
complement representation of - (-27) = 00011011 =+ 27
11100101
=-27 in 2s complement
Now
add 68 and 27
68 0 1 0 0 0 1 0 0
-(-27) + 0 0 0 1 1 0 1 1
95 0 1 0 1 1 1 1 1 1
Which
is equal to +95
Q.33 Divide 
by 
. (4)
Ans:
1
0 1 1 0 1 1 1 0 1 0 0 1
1 0 1
0 0 0 1 1 0
1 0 1
0 0 1
Quotient
-1001
Remainder
-001
Q.34 Prove the following identities
using Boolean algebra:
(i) 
.
(ii) 
.
(iii) 
. (9)
Ans:
(i)
(A+B)(A+AB)C+A(B+C)+AB+ABC
=C(A+B)+A(B+C)
LHS (A+B)(A+A+B)C+AB+AC+AB+ABC
=
(A+B)(1+B)C+AB+ AC+ABC as (A+A=1)
= (A+B).1.C+AB+ AC+ABC
= AB+AC+AB+ AC+ABC
= ABC+AB+ABC+AC+AB+AC
AB(C+1)+AC(B+1) +AB+ AC
= AB+AC+AB+ AC
= C(A+B) + A(B+C) = RHS
Hence Proved
(ii) 
Let
us take 
So
we have 
-------3
Also
= 
By
using DeMorgans Law (AB)=A+B
X
= (A(A+B))=(AA+AB)=(AB)=(A+B) ------1
Now
Y = (B(AB))=[B(A+B)]= [AB+BB]=(AB)=(A+B) ------2
Now
Combining X & Y from 1 & 2 above, we have L.H.S in 3 as :
((A+B)(A+B))
=[AA+BB+AB+AB]
=(AB+AB)
=A
XOR B = RHS
Hence Proved
(iii)
((AB)+A+AB)=0
LHS
= 
since 
= 
since 
= 0 = RHS
Hence Proved
Q.35 A
combinational circuit has 3 inputs A, B, C and output F. F is true for following input combinations
A is False, B is True
A is False, C is True
A, B, C are False
A, B, C are True
(i) Write the Truth table for F. Use the convention True=1 and False = 0.
(ii) Write the simplified expression for F in SOP
form.
(iii) Write the simplified expression for F in POS
form.
(iv) Draw logic circuit using minimum number of
2-input NAND gates. (7)
Ans:
(i) Making the truth table
|
A
|
B
|
C
|
F
|
|
0
|
0
|
0
|
1
|
|
0
|
0
|
1
|
1
|
|
0
|
1
|
0
|
1
|
|
0
|
1
|
1
|
1
|
|
1
|
0
|
0
|
0
|
|
1
|
0
|
1
|
0
|
|
1
|
1
|
0
|
0
|
|
1
|
1
|
1
|
1
|
A
is false b is true For both value
of c F is true.
(ii) Simplified expression for
F can be found by K-map
In
SOP Form
F
= A+BC
(iii) Simplified expression for
F in POS form
I.
In POS Form MINIMIZE ZEROS
F=AB+AC
II.
F=A+BC taking
complement twice
F=(
A+BC)=(A.(BC))
F=F=(A.(BC))
(iv) Logic circuit by using minimum number of
2-input NAND gates
Q.36 Minimise
the logic function
Use
Karnaugh map. Draw the logic circuit for
the simplified function using NOR gates only. (7)
Ans:
F=∏M(1,2,3,8,9,10,11,14).d(7, 15)
F=BD+BC+AC+AB
By Complementing F
F=(BD+BC+AC+AB)
= [(BD)(BC)(AC)(AB)]
= (B+D)(B+C)(A+C)(A+B)
Taking complement twice and
without opening the bracket
F=[(B+D)+(B+C)(A+C)+(A+B)]
The logic circuit for the
simplified function using NOR gates
Q.37 The
capacity of 2K 16 PROM is to be
expanded to 16 K 16. Find the number of PROM chips required and
the number of address lines in the expanded memory. (4)
Ans:
Required capacity =16k x 16
Available chip (PROM) =2k x 16
The no of chip =16k x 16 = 8
2k
x 16
In the chip total word capacity
= 2 x 210
Thus the address line required
for the single chip = 11
In the expanded memory the word
capacity 16k = 214
Now the address lines
required are 14. Among then 11 will be common and 3 will be connected to 3 x8
decoder.
Q.38 Perform
following subtraction
(i) 11001-10110 using 1s complement
(ii) 11011-11001 using 2s complement (8)
Ans:
(i ) 11001
- 10110
1' s Compliment of 10110 = 01001
1 1 0 0 1
+ 0 1
0 0 1
------------------
1 0 0 0 1 0
Add 1
and ignore carry.
Ans is
00011 = 3.
(ii) 11011
11001 = A B
2's
complement of B = 00111
1 1 0 1 1
+ 0 0 1 1 1
1 0 0 0 1 0
Ignore carry to get answer as 00010 = 2.
Q.39 Reduce
the following equation using k-map
(8)
Ans:
Q.40 Write the expression for Boolean function
F (A, B, C) = ∑m
(1,4,5,6,7) in standard POS form.
(8)
Ans:
in standard POS form
F = m1 + m4 +
m5 + m6 + m7
F =
Σm(1,4,5,6,7)
= ∏ M(0,2,3)
= M0
M2 M3
= (A+B+C)(A+
+C)(A++
)
Q.41 Design a 32:1 multiplexer using two 16:1
multiplexers and a 2:1 multiplexer. (8)
Ans:
To design a 32 X 1 MUX using
Two 16 X 1 MUX & one 2 X 1
There are total 32 input lines and
one O/P line. The 2 X 1 MUX will transmit one of the two
I/P to output depending upon its select line M.
For M = 0 upper MUX
( I0
I15 ) will be
selected and M = 1 lower MUX ( I16 I31 ) will be
selected.
Q.42 Implement the
following function using a 3 line to 8 line
decoder.
S (A,B,C) = ∑ m(1,2,4,7)
C (A,B,C) = ∑ m ( 3,5,6,7) (8)
Ans:
S (A,B,C) = m (1,2,4,7)
C (A,B,C) = m (3,5,6,7)
These are full adder's output as sum (S) and carry ( C ). We know that 3 to 8 line decoder generates all
the minterms from 0 to 7. In the decoder shown in the figure, Do correspond to
minterm mo, and so on. So by ORing appropriate outputs of the
decoder we can implement these functions.
Q.43 Perform the following operations using the
2s complement method:
(i) 23 48 (ii) 48 23 (4)
Ans:
(i) 23 - 48
add them
23 0 1 0 1 1 1
- (-
48) + 0 1 0 0 0 0
71 1 0
0 1 1 1
(ii)
48 - 23 = - 48 + (-23)
-48 =
1 1 0 1 0 0 0 0
-23 = 1 1 1 0 1 0 0 1
1 1 0 1 1 1 0 0 1 =
-71
Carry
is discarded
Q.44 Prove the following Boolean identities using the laws of Boolean
algebra:
(i) 
(ii) 
(4)
Ans:
(i) (A+B)(A+C)=A+BC
LHS
AA+AC+AB+BC=A+AC+AB+BC
OR A((C+1)+A(B+1))+BC
OR
A+A+BC
OR A+BC
= RHS
Hence
Proved
(ii)
ABC+ABC+ABC=A(B + C)
LHS
AC(B+B)+AB(C+C)
OR AC+AB
OR A(B+C)= RHS
Hence
Proved
Q.45 The
Karnaugh map for a SOP function is given below in Fig.1. Determine the simplified SOP Boolean
expression. (5)
Ans:
Q.46 A certain memory has
a capacity of 4K8
(i) How many data input and data output lines
does it have?
(ii) How many address lines does it have?
(iii) What is its capacity in
bytes? (5)
Ans:
(i) available
capacity =4Kx8
= 210 x210 x 8
= 212x8
As in the 4Kx8 ,the second number represents the number of bits in
each word so the number of data input lines will be 8(also the data output
lines) .
(ii)
It has total 4K (2 12)
address line which are required to address 212 locations.
(iii)
Its capacity in bytes is 4K
bytes.
Q.47 A
5-bit DAC produces an output voltage of 0.2V for a digital input of 00001. Find the value of the output voltage for an
input of 11111. What is the resolution
of this DAC? (6)
Ans:
For the Digital output of 00001
Output voltage is =0.2 volt =Resolution
The output=.2x31=15.5volts
Resolution=(0.2volt)/(15.5v)x100=1.290
Q.48 An 8-bit successive
approximation ADC has a resolution of 20mV.
What will be its digital output for an analog input of 2.17V? (4)
Ans:
Resolution =20mv
Analog input
=2.17v
Equivalent value=(2.17)/(2.17)=108.5
Equivalent
Binary value=1101100.1
Q.49 A microprocessor uses
RAM chips of 
capacity.
(i)
How many chips will be required and how many address lines
will be connected to provide capacity of 1024 bytes.
(ii)
How many chips will be required to obtain a memory of
capacity of 16 K bytes. (5)
Ans:
( i ) Available chips = 1024 x 1 capacity
Required capacity = 1024 x 8 capacity
Number of address lines are required = 10
(i.e. 1024 = 210 )
As the word capacity is same (
1024 ) so same address lines will be connected to all chips.
( ii )
Q.50 Find
the Boolean expression for logic circuit shown in Fig.1 below and reduce it
using Boolean algebra. (6)
Ans:
Y =
(AB) + (A + B)
= A +
B + AB Using Demorgans Theorem.
= A +
B(1+A)
= A +
B Since 1+A=1
Q.51 Implement the following function using
4-to-1 multiplexer.
(8)
Ans:
Y(A,B,C)=∑(2,3,5,6)
Let us take B,C as
the select bits and A as input. To decide the input we write.
Y = ABC+ABC+ABC+ABC
= 0 if B=0, C=0
= A if B=0, C=1
= 1 if
B=1, C=0
= A if
B=1, C=1
The corresponding implementation is shown in the figure. Thus
0
A 4x1 Y
1 MUX
A
B C
Q.52 Design a mod-12
Synchronous up counter.
(8)
Ans:
Design a mod 12 synchronous
counter using D-flipflops.
I state table
Present
state Next
state Required D
Inputs
|
A
|
B
|
C
|
D
|
A
|
B
|
C
|
D
|
DA
|
DB
|
DC
|
DD
|
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
|
0
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
0
|
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
|
0
|
1
|
1
|
1
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
|
1
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
First draw the state table having present state,
next state and required flip-flop input to give the transition. D flip flop gives
the output same as the next state itself. Then solve by using K maps to find
out DA DB DC DD for all states.
Unused states are 1100,1101,1110,1111 they can
be treated as dont care conditions from the table. Draw Karnaugh-maps for DA,
DB, DC and DD as follows and obtain Boolean
expressions for them.
Logic diagram for mod-12
Synchronous up-counter
Q.53 Find
how many bits of ADC are required to get an resolution of 0.5 mV if the maximum
full scale voltage is 10 V. (8)
Ans:
Resolution=.5mv
Full
scale output=+10v
%resolution
=(5mv)/10x100=0.05%
No
of bits =Log2(2x1000) = 20
Q.54 Convert the decimal number 45678 to its
hexadecimal equivalent number. (4)
Ans:
(45678)10=(B26E)16
16 45678
16 2854 14 E
16 178 6 6
16 11 2 2
0 11 B
(45678)10=(B26E)16
Q.55 Write the truth table of NOR gate. (4)
Ans:
A B F
0 0 1
0 1 0
1 0 0
1 1 0
Q.56 Design a BCD to
excess 3 code converter using minimum number of NAND gates. Hint: use k map techniques. (8)
Ans:
First
we make the truth table
|
BCD no
A B C D
|
EXCESS-3 NO
W X Y Z
|
|
0 0 0 0
|
0 0 1 1
|
|
0 0 0 1
|
0 1 0 0
|
|
0 0 1 0
|
0 1 0 1
|
|
0 0 1 1
|
0 1 1 0
|
|
0 1 0 0
|
0 1 1 1
|
|
0 1 0 1
|
1 0 0 0
|
|
0 1 1 0
|
1 0 0 1
|
|
0 1 1 1
|
1 0 1 0
|
|
1 0 0 0
|
1 0 1 1
|
|
1 0 0 1
|
1 1 0 0
|
Then by using K maps we can have simplified
functions for w, x, y, z as shown below:
NAND
gate implementation for simplified function
W = BD + AD + AB + BC
By complementing twice we get
W = ((BD + AD + AB + BC))
=
((BD) . (AD) . (AB) . (BC))
X = BCD + BD + BC
By complementing twice we get
X = BCD + BD + BC
=
((BCD) . (BD) . (BC))
Y = CD + CD
=
((CD) + (CD))
Z = D
Logic diagram for BCD to excess 3 code converter by using minimum
number of NAND gates
Q.57 With
the help of a suitable diagram, explain how do you convert a JK flipflop to T
type flipflop. (4)
Ans:
Given flip flop is JK flip flop and it is required to
convert JK into T. First we draw the
characteristic table of T flip flop and then relate the transition with
excitation table of JK flip flop.
Now we solve K maps
for J and K by considering T and Q(t) as input.
Logic
diagram convert a JK flipflop to T type flipflop.
Q.58 A
number of 256 x 8 bit memory chips are available. To design a memory organization of 2 K x 8 memory. Identify the requirements of 256 x 8 memory
chips and explain the details. (8)
Ans:
Chips available=256x8
Required
capacity=2048x8
Number of
chips=(2048x8)/(256x8)=8=(256=28)
Address lines required for 2048x8chip=11(2048=211)
Thus the size of the decoder=3x8
Q.59 Convert
to octal. (8)
Ans:
(177.25)10
= ( )8
First we take
integer part
Q.60 Perform the following subtraction using
1s complement
(i) 11001 10110 (ii) 11011 - 11001 (8)
Ans:
(i) 11001 10110 = X Y
X
= 11001
1s complement of Y = 01001
Sum
= 1 00010
End around carry = 1
So X-Y = 00011
(ii) 11011 11001 = X Y
X
= 11011
1s complement of Y = 00110
Sum = 1 00001
End around carry = 1
So X-Y = 00010
Q.61 Prove
the following identities
(i) 
(ii) 
(8)
Ans:
(i) LHS = ABC +
ABC + ABC + ABC
= AC (B + B) + AC (B + B)
= AC + AC [as B+B = 1]
= C (A + A)
= C [as A+A =1]
= RHS.
Hence Proved
(ii)
LHS = AB + ABC + AB + ABC = B + AC
= B (A + A) + AC (B + B)
= B + AC [as B + B = A + A =
1]
= B + AC
= RHS.
Hence Proved
Q.62 Find the boolean expression for the logic
circuit shown below. (8)
Ans:
Output of Gate-1 (NAND) = (AB)
Output of Gate-2 (NOR) = (A+B)
Output of Gate-3 (NOR) = [(AB) +
(A+B)]
Now applying De-Morgans law, (X+Y) = XY
and
(XY) = (X+Y)
[(AB) + (A+B)] = [(AB)] [(A+B)]
= (AB) (A+B)
= AAB + ABB
= ABB
= AB.
Q.63 Reduce
the following equation using k-map
(8)
Ans:
Multiplying the first term by (A+A)
Y = ABCD + ABCD + ABCD + ABCD +
ABCD + ABCD
= 
= BC + BD
Q.64 Implement the following
function using 8 to 1 multiplexer
(8)
Ans:
We will take three variables B,C & D at selection lines and A as
input. Now there are
eight inputs and they
can be 0,1,A or A depending on the Boolean function.
|
|
I0
|
I1
|
I2
|
I3
|
I4
|
I5
|
I6
|
I7
|
|
A
|
0
|
1
|
2
|
3
|
4
|
5
|
6
|
7
|
|
A
|
8
|
9
|
10
|
11
|
12
|
13
|
14
|
15
|
|
|
A
|
1
|
A
|
A
|
0
|
1
|
0
|
A
|
Now, the realization is:
Q.65 (i) How many 
RAM chips are required
to provide a memory capacity of 2048 bytes.
(ii) How many lines of address bus must be used to
access 2048 bytes of memory. How many
lines of these will be common to each chip?
(iii) How many bits must be decoded for chip
select? What is the size of decoder? (8)
Ans:
(i) Available RAM chips = 128 x 8
Required
memory capacity = 2048 x 8
Number of
chips required = (2048 x 8) / (128
x 8)
=
16.
(ii) Chips
available are of 128 x 8 in size. It means that total 128 (27)
locations are there and each location can store 8 bits. Thus the total number
of address lines required to access 128 locations is 7. As seven address lines
can address 27 locations. These seven lines are common to all chips.
Now to access
2048 locations, we require 11 address lines, as 2048 = 211
(iii)
These higher order lines will be applied to decoder input. The number of
inputs to the decoder will be 11 - 7 = 4.
The size of the decoder will be 4x16. These 16 decoder outputs will be
connected to the chip select input of individual chips.
Q.66 How
many bits are required at the input of a ladder D/A converter, if it is
required to give a resolution of 5mV and if the full scale output is +5V. Find the %age resolution. (8)
Ans:
First we find out the ratio of Full scale output to Resolution = 5V
/ 5 mV = 1000.
Now number of bits = log2 1000 =
10.
Percentage Resolution = 5 mV / 5 V * 100 =
0.1%
Q.67 A 6-bit Dual Slope A/D converter uses a
reference of 6V and a 1 MHz
clock. It uses a fixed count of
40 (101000). Find Maximum Conversion
Time. (4)
Ans
The time T1
given by
T1 = 2N
TC where N = no. of
Bits, Tc = time period of clock pulse
Given N = 6, TC =
1/ 1MHz = 1 ľs.
Therefore T1
= 26 X 10 -6 s = 64 ľs.
Q.68 A
2-digit BCD D/A converter is a weighted resistor type with 
Volt, with 
, 
. Find resolution in
Percent and Volts. (5)
Ans
Resolution = 1/22
= 0.25 volts.
As the resolution is
determined by number of input bits of D/A converter; For example two bit
converter has 22 (4) possible output levels, therefore its
resolution is 1 part in 4
In percent it will be
ź X 100 = 25%
In volts, it will be
0.25 volts.
PART III
DESCRIPTIVES
Q.1 Distinguish
between min terms and max terms. (6)
Ans: Distinguish between
Minterms and Maxterms:
(i) Each individual term in standard Sum Of Products form is
called as minterm whereas each individual term in standard Product Of Sums form
is called maxterm.
(ii)
The unbarred letter represent 1s and the barred letter represent 0s in min
terms, whereas the unbarred letter represent 0s and the barred represent 1s
in maxterms.
(iii)
If a system has variables A, B, C then the minterms would be in the form ABC,
whereas the maxterm would be in the form A+B+C.
(iv) The minterm
designation for three variable expression be
Y=∑m (1, 3,
5, 7)
Where the capital ∑
represents the product and m stands for minterms.
Decimal number 1 corresponds to
binary number 001 or C
Decimal number 3 corresponds to
binary number 011 or BC
Decimal number 5 corresponds to
binary number 101 or AC
Decimal number 7 corresponds to
binary number 111 or ABC.
Whereas the Maxterm designation
for three variable expression be
Y=∏M (0, 1, 3, 4)
Where the capital ∏
represents the product and M stands for maxterms.
Decimal 0 means binary 000 and
term is A+B+C
Decimal 1 means binary 001 and
term is A+B+
Decimal 3 means binary 011 and
term is A++
Decimal 4 means binary 100 and
term is+B+C
Q.2 What are universal gates.
Construct a logic circuit using NAND gates only for the expression x = A . (B +
C). (7)
Ans:
Universal Gates: NAND and NOR Gates are known as
Universal gates. The AND, OR, NOT gates can be realized using any of these two
gates. The entire logic system can be
implemented by using any of these two gates.
These gates are easier to realize and consume less power than other
gates.
Construction of a
logic circuit for the expression X = A (B + C) using NAND gates is Shown in fig.4 (b)
Fig.4(b) Logic Diagram for the expression X = A (B + C)
Q.3 Mention the various IC logic families. (7)
Ans:
Various
IC Logic Families: Digital ICs are fabricated by employing either the Bipolar
or the Unipolar Technologies and are referred to as Bipolar Logic Family or
Unipolar Logic Family
I Bipolar Logic
Families:
There are two types
of operations in Bipolar Logic Families
1. Saturated Logic Families
2. Non-saturated Logic Families
1.
Saturated Logic Families: In
Saturated Logic, the transistors in the IC are
driven to
saturation.
(i) Resistor-Transistor Logic (RTL).
(ii) Direct-Coupled Transistor Logic
(DCTL)
(iii) Integrated-Injection Logic (I˛L)
(iv) Diode -Transistor Logic (DTL)
(v) High-Threshold Logic (HTL)
(vi)Transistor-Transistor Logic (TTL)
2. Non-saturated
Logic: In Non-saturated Logic, the transistors are
not driven into saturation.
(i)
Schottky TTL
(ii)
Emitter Coupled Logic (ECL)
II Unipolar Logic
Families:
MOS devices are Unipolar devices and only
MOSFETs are employed in MOS logic
circuits. The MOS logic families are
(i)
PMOS
(ii)
NMOS, and
(iii)
CMOS
while in PMOS only p-channel MOSFETs are used
and in NMOS only n-channel
MOSFETs are used, in complementary MOS
(CMOS), both P and N channel
MOSFETs are employed and are fabricated on
the same silicon chip.
Q.4 What is a half-adder? Explain a
half-adder with the help of truth-table and logic diagram. (10)
Ans:
Half Adder: A logic circuit for
the addition of two one-bit numbers is referred to as an half-adder. The
addition process is illustrated in truth table shown in Table 6.1. Here A and B
are the two inputs and S (SUM) and C (CARRY) are two outputs.
|
A
|
B
|
S
|
C
|
|
0
|
0
|
0
|
0
|
|
0
|
1
|
1
|
0
|
|
1
|
0
|
1
|
0
|
|
1
|
1
|
0
|
1
|
Table 6.1 Truth Table for Half Adder
From the truth table, we obtain the logical
expressions for S and C outputs as
S = B+A
C = AB
The
logic diagram for an Half-adder using gates is shown in fig.6(a)
Fig.6(a) Logic Diagram for an
Half-adder
Q.5 Using a suitable
logic diagram explain the working of a 1-to-16 de multiplexer. (7)
Ans:
Working of a 1-to-16 Demultiplexer: A demultiplexer
takes in data from one line and directs it to any of its N outputs depending on
the status of the selected inputs. If
the number of output lines is N (16), the number of select lines m is given by
2m = N.i.e., 24 = 16.
So, the number of select lines required for a 1-to-16 demultiplexer is
4. Table 7.1 shows the Truth Table of 1-to-16 Demultiplexer. The input can be sent to any of the 16
outputs, D0 to D15.
If DCBA = 0000, the input goes to
D0. If DCBA = 0001, the input goes to D1
and so on.
Fig.7(a) shows the
logic diagram of a 1-to-16 demultiplexer, consists of 8 NOT gates, 16 NAND gates, one data input line(G), 4 select lines
(A,B,C,D) and 16 output lines (D0,
D1, D2 ------D16). The 8 NOT gates prevent
excessive loading of the driving source. One data input line G is implemented
with a NOR gate used as negative AND gate. A low level in each input 
and 
is required to make the output G high. The output G of
enable is one of the inputs to all the 16 NAND gates. G must be high for the
gates to be enabled. If the enable gate is not activated then all sixteen de multiplexer
outputs will be high irrespective of the state of the select lines A,B,C,D.
|
Demulti-plexer
Input
|
Selection Lines
D C B
A
|
Logic
Function
|
Demultiplexer Outputs
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
D11 D12
D13 D14 D15
|
|
0
|
0
0 0 0
|
|
0
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
|
|
1
|
0
0 0 1
|
A
|
1 0 1
1 1 1
1 1 1
1 1 1
1 1 1
1
|
|
2
|
0
0 1 0
|
|
1
1 0 1
1 1 1
1 1 1
1 1 1
1 1 1
|
|
3
|
0
0 1 1
|
B
A
|
1
1 1 0
1 1 1
1 1 1
1 1 1
1 1 1
|
|
4
|
0
1 0 0
|
C
|
1
1 1 1
0 1
1 1 1
1 1 1
1 1 1
1
|
|
5
|
0
1 0 1
|
C A
|
1
1 1 1
1 0 1
1 1 1
1 1 1
1 1 1
|
|
6
|
0
1 1 0
|
C B
|
1
1 1 1
1 1 0
1 1 1
1 1 1
1 1 1
|
|
7
|
0
1 1 1
|
C B A
|
1
1 1 1
1 1 1
0 1 1
1 1 1
1 1 1
|
|
8
|
1
0 0 0
|
D
|
1
1 1 1
1 1 1
1 0 1
1 1 1
1 1 1
|
|
9
|
1
0 0 1
|
D A
|
1
1 1 1
1 1 1
1 1 0
1 1 1
1 1 1
|
|
10
|
1
0 1 0
|
DB
|
1
1 1 1
1 1 1
1 1 1
0 1 1
1 1 1
|
|
11
|
1
0 1 1
|
D B A
|
1
1 1 1
1 1 1
1 1 1
1 0 1
1 1 1
|
|
12
|
1
1 0 0
|
D C
|
1
1 1 1
1 1 1
1 1 1
1 1 0
1 1 1
|
|
13
|
1
1 0 1
|
D C A
|
1
1 1 1
1 1 1
1 1 1
1 1 1
0 1 1
|
|
14
|
1
1 1 0
|
D C B
|
1
1 1 1
1 1 1
1 1 1
1 1 1
1 0 1
|
|
15
|
1
1 1 1
|
D C B A
|
1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 0
|
Table 7.1 Truth Table of 1-to-16
Demultiplexer
Fig.7(a) Logic Diagram of 1-to-16 De multiplexer
Q.6 . With relevant logic diagram and truth table
explain the working of a two input EX-OR gate. (7)
Ans:
Two-Input EX-OR Gate: An Exclusive-OR (EX-OR) gate recognizes words which have an
odd number of ones. Fig.7(b) shows the
logic diagram of an EX-OR gate and Fig.7(c) shows the symbol of an EX-OR Gate.
The upper AND gate gives an output B and the lower
AND gate gives an output A.
Fig.7(b) Logic Diagram of EX-OR Gate
Fig.7(c) Symbol of EX-OR Gate
Therefore, the output
equation becomes Y = B + A = A EX-OR B = A Ĺ
B
If both A and B are
low, the output is low. If either A or B
(not both) are high (and the other is low), the output is high. If both
A and B are high, output is low. Thus
the output is 1 when A and B are different.
Table 7.2 shows the Truth Table for EX-OR gate.
|
A
|
B
|
Y ( B + A )
|
|
0
|
0
|
0
|
|
0
|
1
|
1
|
|
1
|
0
|
1
|
|
1
|
1
|
0
|
Table 7.2 Truth Table of EX-OR Gate
Q.7 With
the help of clocked JK flip flops and waveforms, explain the working of a three
bit binary ripple counter. Write truth table for clock transitions. (14)
Ans:
3-Bit Binary Ripple Counter:
In Ripple Counters, all the Flip-Flops are not
clocked simultaneously and the flip-flops do not change state exactly at the
same time. A 3-bit Binary Counter has maximum of 23 states i.e., 8
states, which requires 3 Flip-Flops. The word Binary Counter means a
counter which counts and produces binary outputs 000,001,010--111.It goes
through a binary sequence of 8 different states (i.e, from 0 to 7). Fig.8(a) shows the
logic circuit of a 3-bit Binary Ripple Counter consisting of 3 Edge Triggered
JK flip-flops. As indicated by small circles at the CLK input of flip-flops,
the triggering occurs when CLK input gets a negative edge. Q0 is the
Least Significant Bit (LSB) and Q2 is the Most Significant Bit
(MSB). The flip-flops are connected in series.
The Q0 output is connected to CLK terminal of second
flip-flop. The Q1 output is connected to CLK terminal of third
flip-flop. It is known as a Ripple Counter because the carry moves through the
flip-flops like a ripple on water.
Working: Initially, CLR is made Low and
all flip-flops Reset giving an output Q = 000. When CLR becomes High, the
counter is ready to start. As LSB receives its clock pulse, its output changes
from 0 to 1 and the total output Q = 001. When second clock pulse arrives, Q0
resets and carries (i.e., Q0 goes from 1 to 0 and, second flip flop
will receive CLK input). Now the output is Q = 010. The third CLK pulse changes
Q0 to 1 giving a total output Q = 011. The fourth CLK pulse causes Q0
to reset and carry and Q1 also resets and carries giving a total
output Q = 100 and the process goes on. The action is shown is Table 8.1.The
number of output states of a counter are known as Modulus (or Mod). A Ripple
Counter with 3 flip-flops can count from 0 to 7 and is therefore, known as
Mod-8 counter.
|
Counter State
|
Q2
|
Q1
|
Q0
|
|
0
|
0
|
0
|
0
|
|
1
|
0
|
0
|
1
|
|
2
|
0
|
1
|
0
|
|
3
|
0
|
1
|
1
|
|
4
|
1
|
0
|
0
|
|
5
|
1
|
0
|
1
|
|
6
|
1
|
1
|
0
|
|
7
|
1
|
1
|
1
|
Table.8.1
Counting Sequence of a 3-bit Binary Ripple Counter
Fig.8(a) Logic Diagram of 3-Bit Binary Ripple Counter
Ripple counters are
simple to fabricate but have the problem that the carry has to propagate
through a number of flip flops. The delay times of all the flip flops are
added. Therefore, they are very slow for some applications. Another problem is
that unwanted pulses occur at the output of gates.
Fig.8(b)
Timing Diagram of 3-bit Binary Ripple Counter
The timing diagram is shown in Fig.8(b).
FF0 is LSB flip flop and FF2 is the MSB flip
flop. Since FF0 receives each clock pulse, Q0 toggles once
per negative clock edge as shown in Fig. 8(b).The remaining flip flops
toggle less often because they receive negative clock edge from preceding flip
flops. When Q0 goes from 1 to 0, FF1 receives a
negative edge and toggles. Similarly, when Q1 changes from 1 to 0, FF2
receives a negative edge and toggles. Finally when Q2 changes
from 1 to 0, FF3 receives a negative edge and toggles. Thus
whenever a flip flop resets to 0, the next higher flip flop toggles.
This counter is known
as ripple counter because the 8th clock pulse is applied, the trailing edge of
8th pulse causes a transition in each flip flop. Q0 goes from High
to Low, this causes Q1 go from High to Low which causes Q2
to go from High to Low which causes Q3 to go from High to Low. Thus
the effect ripples through the counter. It is the delay caused by this ripple
which result in a limitation on the maximum frequency of the input signal.
Q.8 Using D-Flip flops and waveforms explain the working of a
4-bit SISO shift register. (14)
Ans:
Serial In - Serial Out Shift Register: Fig.9(a) shows a 4
bit serial in - serial out shift register consisting of four D flip flops FF0
, FF1 , FF2 and FF3. As
shown it is a positive edge triggered device. The working of this register for
the data 1010 is given in the following steps.
Fig.9(a)
Logic Diagram of 4-bit Serial In Serial Out Shift Register
Fig.9(b)
Output Waveforms of 4-bit Serial-in Serial-out Register
1.
Bit 0 is entered into data input line. D0 =
0, first clock pulse is applied, FF0 is reset and
stores 0.
2.
Next bit 1 is entered. Q0 = 0, since Q0
is connected to D1, D1 becomes 0.
3.
Second clock pulse is applied, the 1 on the input line is
shifted into FF0 because FF0
sets. The 0 which was
stored in FF0 is shifted into FF1.
4.
Next bit 0 is entered and third clock pulse applied. 0 is
entered into FF0, 1 stored in FF0
is shifted to FF1 and 0 stored
in FF1 is shifted to FF2.
5.
Last bit 1 is entered and 4th clock pulse applied. 1 is
entered into FF0, 0 stored in FF0 is
shifted to FF1, 1 stored in FF1 is shifted
to FF2 and 0 stored in FF2 is shifted to FF3.
This completes the serial entry of 4 bit data into the register. Now the
LSB 0 is on the output Q3.
6.
Clock pulse 5 is applied. LSB 0 is shifted out. The next bit
1 appears on Q3 output.
7.
Clock pulse 6 is applied. The 1 on Q3 is shifted
out and 0 appears on Q3 output.
8.
Clock pulse 7 is applied. 0 on Q3 is shifted out.
Now 1 appears on Q3 output.
9.
Clock pulse 8 is applied. 1 on Q3 is shifted out.
10.
When the bits are being shifted out (on CLK pulse 5 to 8)
more data bits can be
entered in.
Q.9 With the help of R-2R binary ladder,
explain the working of a 4-bit D/A converter (14)
Ans:
R-2R Ladder network
method: In
a R-2R ladder network method of digital to analog conversion, irrespective of
number of bits of the DAC only two convenient values of resistors are needed in
the ratio of 1:2 as depicted in fig 10(a). An R-2R Ladder Network based on constant reference current. In the
circuit of fig 10(a) points G are actual ground and points G' are virtual ground.
Therefore the potential at all the Gs and Gs is
zero. Between ground (actual or
virtual) and node A there are two resistors each of value 2R in parallel.
Therefore this resultant resistance between ground and node A is R and the
current through each of the 2R resistance connected to node A must be same. Let
us say this current is I. Then the current flowing from A to B through the
resistor R is 2I. Then the total resistance from ground to node B through the
node A becomes 2R. Also the resistance directly connected between ground and B
is also 2R. So between the node B and ground there are two equal resistances in
parallel each of value 2R. Therefore, the resultant resistance is R and the
current approaching to node B from both sides must be equal. Since current
approaching from the side of node A is 2I,
therefore the current approaching to the node B from the resistor 2R
under it must also be 2I. Hence the total current approaching the node C from
the side of node B is 4I. On the basis of the same logic the current
approaching to node D from the side of node C must be 8I and the current
approaching it form the 2R resistor under node D should also be 8I.
Fig.10(a) R-2R Ladder
Network D/A Converter
Whenever any of the bit or bits
of the digital input word D3 D2 D1D0
is high, the corresponding transistor switch is ON i.e. connected to
virtual ground and the current of that vertical branch of the ladder comes from
the output, otherwise the current of the vertical branch comes directly from
the actual ground without any effect on the output. Hence the output current
(lout) gives the analog current value corresponding to the digital input word.
This analog current gets converted to the analog voltage Vo.
An R-2R 4-Bit Ladder Network DAC based on reference voltage: An R-2R 4-bit Ladder
Network D/A Converter is shown in fig. 10(b) 
Fig.10(b) R-2R 4-bit
Ladder Network D/A Converter
Proof:
Step 1: If the digital value
to be converted to analog value is 0001 i.e.D0
is on the high side connected to Vref while D1, D2,
and D3 are connected to ground. Then the circuit redrawn as shown
inFig.10(c).
Fig.10(c) R-2R Ladder Network D/A Converter when D0
is connected to Vref and D1,D2,D3
are connected to ground
Applying Thevenins theorem at X1,X1
, the circuit of fig.10(c) becomes the equivalent circuit shown in
fig.10(d) 
Fig.10(d) R-2R Ladder Network D/A Converter when Thevenins
Theorem applied at X1 and X1
Again
Applying Thevenins Theorem at X2,X2, then the circuit
of fig.10(d) becomes the equivalent circuit shown in fig.10(e).
Fig.10(e) R-2R Ladder Network D/A
Converter when Thevenins Theorem applied at X2 and X2
Again Applying Thevenins
Theorem at X3,X3 the circuit of fig.10(e) becomes the
equivalent circuit shown in fig.10(f):
Fig.10(f)
R-2R Ladder Network D/A Converter when Thevenins Theorem applied at X3
and X3
Once
Again applying Thevenins theorem at section X4, X4 the
circuit of fig.10(f) finally becomes the equivalent circuit shown in fig.10(g).
Fig.10(g)
R-2R Ladder Network D/A Converter when Thevenins Theorem applied at X4
and X4
Step 2: If D1 is
high (connected to Vref) and D0, D2, D3 are
all low (connected to ground), then the circuit becomes:
Fig.10(h)
R-2R Ladder Network D/A Converter when D1 is connected to Vref
and
D0,D2,D3
are connected to ground
Applying Thevenins
Theorem, three times and reducing the circuit each time at sections X1,
X2, X3 we finally get the circuit as shown in fig.10(i).
Fig.10(i) Equivalent
Circuit when D1 is connected to Vref D0,D2,D3
are connected to ground
Step 3: Repeating the same exercise of D2 High and other
bits Low, we get the finally reduced Circuit as shown in fig.10(j).
Fig.10(j) Equivalent Circuit when D2 is connected
to Vref D0,D1,D3 are connected
to
ground
Step 4: Repeating the same for D3 High and other bits
Low, we can reduce the circuit shown in fig.10(k).
Fig.10(k) Equivalent Circuit when D3 is connected to Vref
D0,D1,D2 are connected to ground
Step 5: Compiling the reduced circuits of the above four steps by
applying Superposition Theorem, then the network of fig 10(g),10(i),10(j),10(k) becomes the
equivalent circuit shown in fig.10(m).
Fig.10(m) Equivalent circuit by applying Superposition
Theorem for the circuits of
fig.10(g),10(i),10(j),10(k)
Hence the derived
equivalent circuit of the R-2R ladder network proves that the bits of the input
digital word D3, D2, D1, D0 receive
the applied voltages as per their binary weights and we get the corresponding
analog value at Vo. Therefore,
If Rf is also
selected equal to 2R, then
VO is
independent of the numerical values of R.
Thus any convenient value of R & 2R can be taken for the design of
the D/A converter. The maximum output
analog voltage is nearly equal to Vref. The actual values of R-2R resistors influence
only the maximum current handled by the op-amp.
Voltage resolution of n-bit ladder network DAC is Vref/2n
Q.10 With relevant diagram explain the working
of master-slave JK flip flop. (9)
Ans:
Master-Slave J-K FLIP-FLOP: A
master-slave J-K FLIP-FLOP is a cascade of two S-R FLIP-FLOPS.
One of them is known as Master and the other one is slave. Fig.11(a) shows the logic circuit. The master is positively clocked. Due to the presence of inverter, the slave is
negatively clocked. This means that when clock is high, the master is active
and the slave is inactive.
When the clock is
low, the master is inactive and the slave is active. Fig.11(b) shows the
symbol. This is a level clocked Flip-Flop.
When clock is high, any changes in J and K inputs can affect S and R
outputs. Therefore, J and K are kept
constant during positive half of clock.
When clock is low, the master is inactive and J and K inputs can be
allowed to be changed. The different conditions are Set, Reset, and Toggle. The
race condition is avoided because of feedback from slave to master and the
slave being inactive during positive half of clock.
(i)
SET State: Assume that Q is low (and 
is high). For high J, low K and high CLK, the Master
goes to SET state giving High S and Low R.
Since Slave is inactive, Q and do not change.
When CLK becomes Low, the Slave becomes to Set state giving High Q (and low ).
(ii)
RESET State: At the end of Set State Q is
High (and low). Now if J is low, K is high and CLK is high, the
Master Resets giving Low S and High R. Q and do not change
because Slave is inactive. When CLK becomes Low, the Slave becomes active and
resets giving Low Q (and High ).
(iii) Toggle State:
If
both J and K are High, the Slave copies the Master. When CLK is High, the Master toggles once.
Then the Slave toggles once when CLK is low.
If the Master toggles into Set state, the slave copies the Master and
toggles into Set state. If the Master
toggles into Reset state, the slave again copies the Master and toggles into
Reset state. Since the second FLIP-FLOP simply follows the first one, it is
referred to as the slave and the first one as the master. Hence,
this configuration is referred to as master-slave(M-S) FLIP-FLOP.
Truth Table of JK Master Slave
Flip-Flop in Table 11.1 shows that a Low PR and Low CLR can cause race
condition. Therefore, PR and CLR are kept High when inactive. To clear, we make
CLR Low and to preset we make PR Low. In both cases we change them to High when
the system is to be run.
Low J and Low K produce inactive
state irrespective of clock input. If K
goes High, the next clock pulse resets the Flip-Flop. If J goes High by itself,
the next clock pulse sets the Flip-Flop. When both J and K are High, each clock
pulse produces one toggle.
Fig.11(a)
Logic Diagram of Master-Slave J-K FLIP-FLOP
Fig.11(b)
Logic Symbol of Master-Slave J-K FLIP-FLOP
|
|
|
Inputs
|
|
|
Output
|
|
PR
|
CLR
|
CLK
|
J
|
K
|
Q
|
|
0
|
0
|
X
|
X
|
X
|
Race
Condition
|
|
0
|
1
|
X
|
X
|
X
|
1
|
|
1
|
0
|
X
|
X
|
X
|
0
|
|
1
|
1
|
X
|
0
|
0
|
No
change
|
|
1
|
 1
|
   
|
0
|
1
|
0
|
|
1
|
1
|
 
|
1
|
0
|
1
|
|
1
|
1
|
  
|
1
|
1
|
Toggle
|
Table
11.1 Truth Table of JK Master-Slave Flip-Flop
Q.11 Compare
the memory devices RAM and ROM. (5)
Ans:
Comparison
of Semi-conductor Memories ROM and RAM
The advantages of ROM are:
1. It is cheaper than RAM.
2. It is non-volatile.
Therefore, the contents are not lost when power is switched off.
3.It is available in larger
sizes than RAM. '
4. It's contents are always
known and can be easily tested.
5. It does not require
refreshing.
6. There is no chance of any
accidental change in its contents.
The advantages of RAM are:
1. It can be updated and
replaced.
2. It can serve as temporary
data storage.
3. It does not require lead time
(as in ROM) or programming time (as in PROM).
4. It does not
require any programming equipment
Q.12 State and prove Demorgans laws. (5)
Ans:
De
Morgan's Theorems:
(i)
Statement of First Theorem:
.
Proof: The two sides of the equation 
is
represented by logic diagrams shown in fig.3 (a) & 3(b)
Fig.3(a) Logic diagram for Fig.3(b) Logic diagram for 
The equality of the
logic diagrams of fig.3 (a) & 3(b) is proved by the truth table shown in
table 2(c)
|
Inputs
|
|
Intermediate
|
Values
|
|
Outputs
|
|
|
A
|
B
|
A + B
|
|
|
|
|
|
0
|
0
|
0
|
1
|
1
|
1
|
1
|
|
0
|
1
|
1
|
1
|
0
|
0
|
0
|
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
|
1
|
1
|
1
|
0
|
0
|
0
|
0
|
Table 2(c)
(ii)
Statement of second
theorem: 
Proof: The two sides of the equation is represented by the logic diagrams shown in
fig.3(c) & 3(d).
Fig.3(c) Logic diagram for Fig.3(d) Logic
diagram for 
The equality of the
logic diagrams of fig.3(c) & 3(d) is proved by the truth table shown in
table 2(d)
|
Inputs
|
Intermediate Values
|
Outputs
|
|
A
|
B
|
A .B
|
|
|
|
+
|
|
0
|
0
|
0
|
1
|
1
|
1
|
1
|
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
|
1
|
0
|
0
|
0
|
1
|
1
|
1
|
|
1
|
1
|
1
|
0
|
0
|
0
|
0
|
Table 2(d)
Q.13 Discuss in detail, the working of Full Adder logic circuit and extend
your discussion to explain a binary adder, which can be used to add two binary
numbers. (14)
Ans:
Full-Adder: A half-adder has
only two inputs and there is no provision to add a carry from the lower order
bits when multibit addition is performed.
For this purpose, a third input terminal is added and this circuit is
used to add An, Bn, and Cn-1, where An
and Bn are the nth order bits of the numbers, A and B respectively and Cn-1 is the carry generated from the
addition of (n-1)th order bits. This
circuit is referred to as full-adder and its truth table is given in Table 5.1
|
 Inputs
An Bn Cn-1
|
Outputs
Sn
Cn
|
|
0 0 0
|
0 0
|
|
0 0 1
|
1 0
|
|
0 1 0
|
1 0
|
|
0 1 1
|
0 1
|
|
1 0 0
|
1 0
|
|
1 0 1
|
0 1
|
|
1 1 0
|
0 1
|
|
1 1 1
|
1 1
|
Table 5.1 Truth Table of a Full-Adder
The K-maps for the
outputs Sn and Cn are given in Fig.5(a) and Fig.5(b)
respectively and the minimized expressions are given by
Sn = 
Bn
+ 
Cn-1
+ An + An Bn Cn-1
Cn = An
Bn + Bn Cn-1 + An Cn-1
Bn An
Bn Bn
____
Cn-1
Cn-1
Fig.5(a)
K-map for Sn
Fig.5(b)
K-map for Cn
The logic diagrams for the Sn
and Cn are shown in fig.5(c) & fig.5(d).
Fig.5(c) NAND-NAND Realization of Sn
Fig.5(d) NAND-NAND Realization of Cn
Binary Adder: The full adder forms the sum of two bits and a previous
carry. Two binary numbers of n bits each can be added by means of Binary Adder.
If A = 1011 and B = 0011, whose sum is S = 1110. When pair of bits is added
through a full-adder, the circuit produces a carry to be used with the pair of
bits one significant position higher. This is shown in Table 5.2
The bits are added
with full-adders, starting from the Least Significant Position (subscript 1),
to form the sum bit and carry bit. The
input carry C1 in the Least Significant position must be 0. The value of Ci+1
in a given significant position is the output carry of the full-adder. This
value is transferred into the input carry of the full-adder that adds the bits
one higher significant position to the left. The sum bits are thus generated
starting form the rightmost position and are available as soon as the
corresponding previous carry bit is generated
|
Subscript
i
|
4
|
3
|
2
|
1
|
|
Full-Adder
|
|
Input
Carry
|
0
|
1
|
1
|
0
|
Ci
|
Z
|
|
Augend
|
1
|
0
|
1
|
1
|
Ai
|
X
|
|
Addend
|
0
|
0
|
1
|
1
|
Bi
|
Y
|
|
Sum
|
1
|
1
|
1
|
0
|
Si
|
S
|
|
Output
Carry
|
0
|
0
|
1
|
1
|
Ci+1
|
C
|
Table 5.2 Truth Table for Binary
Adder
A Binary Parallel
Adder is a digital function that produces the arithmetic sum of two binary
numbers in parallel. It consists of full-adders connected in cascade, with the
output carry from one full-adder connected to the input carry of the next
full-adder. Fig.5(e) shows a 4-bit Binary Parallel Adder. The augend bits of A
and the addend bits of the B are designated by subscript numbers from right to
left, with subscript 1 denoting the low-order bit. The carries are connected in
a chain through the full-adders. The input carry to the adder is C1
and the output carry is C5. The S outputs generate the required sum
bits.
Fig.5(e) 4-bit Binary Parallel Adder using Full-Adders
Q.14 What is a decoder? Draw the logic circuit of a 3 line to 8 line decoder
and explain its working. (7)
Ans:
Decoder: A Decoder is a combinational logic circuit
that converts Binary words into alphanumeric characters. Thus the inputs to a
decoder are the bits 1, 0 and their combinations. The output is the corresponding decimal
number. It converts binary information
from n input lines to a maximum of 2n unique output lines. If
the n-bit decoded information has unused or don't-care combinations, the
decoder output will have less than 2n outputs.
Working: The logic circuit of a 3 line to 8 line decoder is shown
in fig.6 (a). The three inputs (x, y, z) are decoded into eight outputs (from D0
to D7), each output representing one of the minterms of the 3-input
variables. The three inverters provide the complement of the inputs, and each
one of the eight AND gates generate one of the minterms. A particular
application of this decoder is a binary-to-octal conversion. The input
variables may represent a binary number, and the outputs will then represent
the eight digits in the octal number system. However, a 3-to-8 line decoder can
be used for decoding any 3-bit code to provide eight outputs, one for each
element of the code.
The operation of the
decoder may be verified from its input-output relationships shown in Table
6.1.The table shows that the output variables are mutually exclusive because
only one output can be equal to 1 at any one time. Consider the case when X=0,
Y=0 and Z=0, the output line D0 (X, Y, Z) is equal to 1
represents the minterm equivalent of the binary number presently available in
the input lines.
|
Inputs
X Y
Z
|
Outputs
D0 D1 D2 D3 D4 D5 D6 D7
|
|
0 0
0
|
1 0 0 0 0 0 0 0
|
|
0 0
1
|
0 1 0 0 0 0 0 0
|
|
0 1
0
|
0 0 1 0 0 0 0 0
|
|
0 1
1
|
0 0 0 1 0 0 0 0
|
|
1 0
0
|
0 0 0 0 1 0 0 0
|
|
1 0
1
|
0 0
0 0 0 1 0 0
|
|
1 1
0
|
0 0 0 0 0 0 1 0
|
|
1 1
1
|
0 0 0 0 0 0 0 1
|
Table 6.1 Truth Table of 3-to-8 line
Decoder
Fig.
6(a) Logic Circuit of 3-to-8 line Decoder
Q.15 What is an encoder?
Draw the logic circuit of Decimal to BCD
encoder and explain its working. (7)
Ans:
Encoder: An Encoder is a
combinational logic circuit which converts Alphanumeric characters into Binary
codes. It has 2n (or less) input lines and n output lines. An Encoder may be Decimal to Binary,
Hexadecimal to Binary, Octal to BCD etc.
Decimal
to BCD Encoder: This encoder has 10
inputs (for decimal numbers 0 to p) and 4 outputs for the BCD number. Thus it
is a 10 line to 4 line encoder. Table
6(a) lists the decimal digits and the equivalent BCD numbers. From the table, we
can find the relationship between decimal digit and BCD bit. MSB of BCD bit is Y3. For decimal digits 8 or 9, Y3 = 1. Thus we can write
OR expression for Y3 bit as
Y3 = 8 + 9
Similarly , Bit Y2 is 1
for decimal digits 4,5,6 and 7. Thus we can write OR
expression
Y2 = 4
+ 5 + 6 + 7
Y1 = 2 + 3 + 6 + 7
Yo
= 1 + 3 + 5 + 7 + 9
The logic circuit for
the expressions (Y0, Y1, Y2, Y3) is shown in fig. 6(b). When a High appears on
any of input lines the corresponding OR gates give the BCD output. For e.g., if decimal input is 8, High
appears only on output 3 (and LOW on Y0, Y1 , Y2),
thus giving the BCD code for decimal 8 as 1000. Similarly, if decimal input
is 7, then High appears on outputs Y0, Y1, Y2
(and LOW on Y3), thus giving BCD output as 0111.
|
Decimal Digit
|
BCD Code
Y3 Y2 Y1 Y0
|
|
0
|
0 0 0 0
|
|
1
|
0 0 0 1
|
|
2
|
0 0 1 0
|
|
3
|
0 0 1 1
|
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4
|
0 1 0 0
|
|
5
|
0 1 0 1
|
|
6
|
0 1 1 0
|
|
7
|
0 1 1 1
|
|
8
|
1 0
0 0
|
|
9
|
1 0 0 1
|
Fig.6(b)
Logic diagram for Decimal to BCD Encoder
Q.16 What
is a flip-flop? What is the difference between a latch and a flip-flop? List
out the application of flip-flop. (4)
Ans:
Flip-Flop: A flip-flop is a basic memory element used to store one bit
of information. Both Flip-flops and latches are bistable logic circuits and can
reside in any of the two stable states due to a feedback arrangement. The main
difference between them is in the method used for changing the state.
Applications of Flop-Flops:
(1)
Bounce elimination switch
(2)
Parallel Data Storage in Registers
(3)
Transfer of Data from one bit to another.
(4)
Counters
(5)
Frequency Division
Q.17 Draw
the circuit diagram of a Master-slave J-K flip-flop using NAND gates. What is
race around condition? How is it eliminated in a Master-slave J-K flip-flop. (10)
Ans:
Logic Diagram of Master-Slave J-K Flip-Flop using NAND
Gates: Fig.7(a)
shows the
logic diagram of Master-Slave J-K Flip-Flop using NAND gates.
Fig.7(a) Logic Diagram of Master-Slave J-K FLIP-FLOP
The Race-around
Condition:
The
difficulty of both inputs 1 (S = R = I) being not allowed in an S-R Flip-Flop
is eliminated in a J-K Flip-Flop by using the feedback connection from
outputs to the inputs of the gates. In R-S Flip-Flop, the inputs do not change
during the clock pulse (CK = 1), which is not true in J-K Flip-Flop
because of the feedback connections. Consider that the inputs are J = K
= 1 and Q = 0 and a pulse as shown in Fig. 7(b) is applied at the
clock input. After a time interval ∆t equal to the propagation delay
through two NAND gates in series, the output will change to Q = 1.
Now we have J = K = 1 and Q = 1 and
after another time interval of ∆t the output will change back to Q =
O. Hence, for the duration tp of the clock pulse, the output
will oscillate back and forth between 0 and 1. At the end of the clock pulse,
the value of Q is uncertain. This situation is referred to as the race-around condition.The
race-around condition can be
avoided if tp
< ∆t < T. However, it may be difficult to satisfy this
inequality because of very small propagation delays in ICs. A more practical
method of overcoming this difficulty is the use of the master-slave (M-S) configuration.
Fig.7 (b) a Clock Pulse
A master-slave J-K
Flip-Flop is a cascade of two S-R Flip-Flops with feedback from the outputs of
the second to the inputs to the first as illustrated in Fig.7(a). Positive
clock pulses are applied to the first Flip-Flop and the clock pulses are
inverted before these are applied to the second Flip-Flop. When CK=1, the first
Flip-Flop is enabled and the outputs QM and 
respond to their
inputs J and K according the Table 7.1. At this time, the second Flip-Flop is
inhibited because its clock is LOW (
= 0). When CK goes LOW ( = 1), the first Flip-Flop is inhibited and the second
Flip-Flop is enabled, because now its clock is HIGH ( = 1). Therefore, the outputs Q and 
Follow the outputs QM and 
respective
(second and third rows of Table 7.1). Since the second Flip-Flop simply follows
the first one, it is referred to as the Slave and the first one as the Master.
Hence, this configuration is referred to as Master-Slave Flip-Flop. In this
circuit, the inputs to the gates G3M and G4M do not
change during the clock pulse, therefore the Race-around condition does not
exist. The state of the Master-Slave Flip-Flop changes at the negative
transition (trailing end).
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|
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Inputs
|
|
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Output
|
|
PR
|
CLR
|
CLK
|
J
|
K
|
Q
|
|
0
|
0
|
X
|
X
|
|
